Power efficient processor architecture and the cell processor

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2005, Pages 258-262

  Hofstee, H Peter ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

IBM (CO); PROCESSOR ARCHITECTURE; SONY GROUP (CO); TOSHIBA (CO);

ENERGY EFFICIENCY; INFORMATION TECHNOLOGY;

COMPUTER ARCHITECTURE;

EID: 27644567646     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2005.26     Document Type: Conference Paper

References (6)

1. H. P. Hofstee, "Power-Constrained Microprocessor Design", 2002 IEEE International Conference on Computer Design, Sep. 2002, pp. 14-16.
2. nd Annual International Symposium on Microarchitecture, (MICRO-32) Nov. 1999, pp. 2-.
3. H. P. Hofstee, "Future Microprocessors and Off-Chip SOP Interconnect," IEEE Transactions on Advanced Packaging, Vol. 27, No. 2, May 2004, pp.301-303.
4. th Annual IEEE/ACM International Symposium on Microarchitecture 2002. pp. 333-344.
5. D. Pham, S. Asano, M. Bolliger, M. N. Day, H. P. Hofstee, C. Johns, J. Kahle, A. Kameyama, J. Keaty, Y. Masubuchi, M. Riley, D. Shippy, D. Stasiak, M. Suzuoki, M. Wang, J. Warnock, S. Weitzel, D. Wendel, T. Yamazaki, K. Yazawa, "The Design and Implementation of a First-Generation CELL Processor," to appear: IEEE International Solid-State Circuits Symposium, Feb. 2005.
6. B. Flachs, S. Asano, S. H. Dhong, H. P. Hofstee, G. Gervais, R. Kim, T. Le, P. Liu, J. Leenstra, J. Liberty, B. Michael, H-J. Oh, S. M. Mueller, O. Takahashi, A. Hatakeyama, Y. Watanabe, N. Yano. "The Microarchitecture of the Streaming Processor for a CELL Processor," to appear: IEEE International Solid-State Circuits Symposium, Feb. 2005.