Hierarchical interconnects for on-chip clustering

Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2002

Volumn , Issue , 2002, Pages 602-609

  Aggarwal, A ^a   Franklin, M ^a  

^a UNIVERSITY OF MARYLAND   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 33745778388     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2002.1015559     Document Type: Conference Paper

References (14)

1. A. Aggarwal and M. Franklin, "An Empirical Study of the Scalability Aspects of Instruction Distribution Algorithms for Clustered Processors," Proc. International Symp. on Performance Analysis of Systems and Software (ISPASS '01), 2001.
2. A. Baniasadi and A. Moshovos, "Instruction Distribution Heuristics for Quad-Cluster, Dynamically-Scheduled, Superscalar Processors," Proc. International Symp. on Microarchitecture (MICRO-33), 2000.
3. R. Canal, J. M. Parcerisa and A. Gonzalez, "Dynamic Cluster Assignment Mechanisms," Proc. Int. Symp. on High-Performance Computer Architecture (HPCA-6), 2000.
4. R. Canal, J. M. Parcerisa and A. Gonzalez, "Dynamic Code Partitioning for Clustered Architectures," International Journal of Parallel Programming, 2000.
5. K. Hwang, "Advanced Computer Architecture," McGraw-Hill, 1992.
6. K. Kailas, K. Ebcioglu, and A. Agrawala, "CARS: A New Code Generation Framework for Clustered ILP Processors," Proc. 7th International Symposium on High Performance Computer Architecture (HPCA-7), pp.133-143, 2001.
7. D. Leibholz and R. Razdan, "The Alpha 21264: A 500 MHz Out-of-Order Execution Microprocessor," Proc. Compcon, pp. 28-36, 1997.
8. S. Palacharla, N. P. Jouppi, and J. E. Smith, "Complexity-Effective Superscalar Processors," Proc. 24th Annual International Symposium on Computer Architecture, pp. 206-218, 1997.
9. N. Rangananathan and M. Franklin, "An Empirical Study of Decentralized ILP Execution Models," Proc. International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-VIII), 1998.
10. E. Rotenberg, S. Bennett, and J. E. Smith, "Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching," Proc. 29th International Symposium on Microarchitecture, 1996.
11. E. Rotenberg, Q. Jacobson, Y. Sazeides, and J. Smith, "Trace Processors," Proc. 30th International Symposium on Microarchitecture, 1997.
12. S. S. Sastry, S. Palacharla, and J. E. Smith, "Exploiting Idle Floating-Point Resources For Integer Execution," Proc. Intl. Conf. on Programming Lang. Design and Implementation, 1998.
13. K. C. Yeager, "The MIPS R10000 Superscalar Microprocessor," IEEE Micro, pp. 28-40, April 1996.
14. The National Technology Roadmap for Semiconductors, Semiconductor Industry Association, 1999.