-
1
-
-
0035271157
-
Design issues for high performance active routers
-
Mar
-
T. Wolf and J. Turner, "Design issues for high performance active routers," IEEE Journal on Selected Areas of Communications - Special Issue on Active and Programmable Networks, vol. 19, no. 3, pp. 404-409, Mar. 2001.
-
(2001)
IEEE Journal on Selected Areas of Communications - Special Issue on Active and Programmable Networks
, vol.19
, Issue.3
, pp. 404-409
-
-
Wolf, T.1
Turner, J.2
-
2
-
-
0033681846
-
High level estimation of the area and power consumption of on-chip interconnects
-
Sept
-
D. Langen, A. Brinkmann, and U. Rückert, "High Level Estimation of the Area and Power Consumption of On-Chip Interconnects," in Proceedings of the 13th Annual IEEE International ASiC/SOC Conference, Sept. 2000, pp. 297-301.
-
(2000)
Proceedings of the 13th Annual IEEE International ASiC/SOC Conference
, pp. 297-301
-
-
Langen, D.1
Brinkmann, A.2
Rückert, U.3
-
3
-
-
0030701044
-
The power analysis of interconnect structures
-
Sept
-
Y. Zhang, W. Ye, R. Owens, and M. Irwirt, "The Power Analysis of Interconnect Structures," in Proceedings of the ASIC'97 Conference, Sept. 1997.
-
(1997)
Proceedings of the ASIC'97 Conference
-
-
Zhang, Y.1
Ye, W.2
Owens, R.3
Irwirt, M.4
-
4
-
-
0032259264
-
An alternative architecture for on-chip global interconnects: Segmented bus power modeling
-
Nov
-
Y. Zhang, W. Ye, and M. lrwin, "An Alternative Architecture for On-Chip Global Interconnects: Segmented Bus Power Modeling" in Proceedings of the 36th Asilomar Conference on Signals, Systems, and Computers, Nov. 1998.
-
(1998)
Proceedings of the 36th Asilomar Conference on Signals, Systems, and Computers
-
-
Zhang, Y.1
Ye, W.2
Irwin, M.3
-
5
-
-
85008008992
-
Interconnect architecture exploration for low-energy reconfigurable single-chip dsps
-
H. Zhang, M. Wan, V. George, and J. Rabaey, "Interconnect Architecture Exploration for Low-Energy Reconfigurable Single-Chip DSPs," in Proceedings of the IEEE Computer Workshop on VLSI'99, 1999.
-
(1999)
Proceedings of the IEEE Computer Workshop on VLSI'99
-
-
Zhang, H.1
Wan, M.2
George, V.3
Rabaey, J.4
-
6
-
-
0034848112
-
Route packets, not wires: On-chip interconnection networks
-
W.J. Dally and B. Towles, "Route packets, not wires: On-chip interconnection networks," in Proceedings of DAC 2001, 2001, pp. 684-689.
-
(2001)
Proceedings of DAC
, vol.2001
, pp. 684-689
-
-
Dally, W.J.1
Towles, B.2
-
7
-
-
0034516483
-
Virtual data space - Load balancing for irregular applications
-
T. Decker, "Virtual data space - load balancing for irregular applications," Parallel Computing, vol. 26, no. 13-14, pp. 1825-1860, 2000.
-
(2000)
Parallel Computing
, vol.26
, Issue.13-14
, pp. 1825-1860
-
-
Decker, T.1
-
9
-
-
0033658337
-
VLSI layout and packaging of butterfly networks
-
July
-
C,-H. Yeh, B. Parhami, E. A. Varvarigos, and H. Lee, "VLSI layout and packaging of butterfly networks," in Proc, of the 12th ACM Symp, on Parallel Algorithms and Architectures (SPAA), July 2000, pp. 196-205.
-
(2000)
Proc, of the 12th ACM Symp, on Parallel Algorithms and Architectures (SPAA)
, pp. 196-205
-
-
Yeh, C.-H.1
Parhami, B.2
Varvarigos, E.A.3
Lee, H.4
-
12
-
-
84949431279
-
Aktive router: Eìn hard- warekonzept für storage area networks
-
Nov
-
A. Brinkmann, D. Langen, and U. Rückert, "Aktive Router: Eìn Hard- warekonzept für Storage Area Networks," in Proceedings of the ITG Workshop Mikroelekironik für die Informationstechnik, Nov. 2000, pp. 41-46.
-
(2000)
Proceedings of the ITG Workshop Mikroelekironik für Die Informationstechnik
, pp. 41-46
-
-
Brinkmann, A.1
Langen, D.2
Rückert, U.3
-
14
-
-
47249161003
-
Simlab - A simulation environment for storage area networks
-
Feb
-
P. Berenbrink, A. Brinkmann, and C. Scheideler, "Simlab - a simulation environment for storage area networks," in Proceedings of the 9th Euromìcro Workshop on Parallel and Distributed Processing, Mantova, Italy, Feb. 2001, pp. 227-234.
-
(2001)
Proceedings of the 9th Euromìcro Workshop on Parallel and Distributed Processing, Mantova, Italy
, pp. 227-234
-
-
Berenbrink, P.1
Brinkmann, A.2
Scheideler, C.3
-
16
-
-
0031073176
-
Intelligent ram (iram): Chips that remember and compute
-
Feb
-
D. Patterson, T. Anderson, N. Cardwell, R. Fromm, K. Keeton, C. Kozyrakis, R. Thomas, and K. Yelick, "Intelligent RAM (IRAM): Chips that Remember and Compute," in Proceedings of the 1997 IEEE International Solid-Stale Circuits Conference. San Francisco, CA, Feb. 1997.
-
(1997)
Proceedings of the 1997 IEEE International Solid-Stale Circuits Conference. San Francisco, CA
-
-
Patterson, D.1
Anderson, T.2
Cardwell, N.3
Fromm, R.4
Keeton, K.5
Kozyrakis, C.6
Thomas, R.7
Yelick, K.8
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