-
1
-
-
0032027787
-
0.15 μm RF CMOS technology compatible with logic CMOS for low-voltage operation
-
Mar.
-
M. Saito, M. Ono, R. Fuzimoto, and T. Yostitomi, "0.15 μm RF CMOS technology compatible with logic CMOS for low-voltage operation," IEEE Trans. Electron Devices, vol. 45, pp. 737-741, Mar. 1998.
-
(1998)
IEEE Trans. Electron Devices
, vol.45
, pp. 737-741
-
-
Saito, M.1
Ono, M.2
Fuzimoto, R.3
Yostitomi, T.4
-
2
-
-
0002450166
-
Process outlook for analog and RF applications
-
Dec.
-
J. J. P. Bruines, "Process outlook for analog and RF applications," Microelectron. Eng., vol. 54, pp. 35-48, Dec. 2000.
-
(2000)
Microelectron. Eng.
, vol.54
, pp. 35-48
-
-
Bruines, J.J.P.1
-
3
-
-
0033719805
-
The effect of scaling on the performance of small signal MOS amplifiers
-
May
-
C. Fiegna, "The effect of scaling on the performance of small signal MOS amplifiers," in Proc. ISCAS 2000, May 2000, pp. 733-736.
-
(2000)
Proc. ISCAS 2000
, pp. 733-736
-
-
Fiegna, C.1
-
4
-
-
0033325117
-
Device issues in the integration of analog/RF functions in deep sub-micron digital CMOS
-
Dec.
-
D. Buss, "Device issues in the integration of analog/RF functions in deep sub-micron digital CMOS," in IEDM Tech. Dig., Dec. 1999, pp. 423-426.
-
(1999)
IEDM Tech. Dig.
, pp. 423-426
-
-
Buss, D.1
-
5
-
-
0034453378
-
CMOS device optimization for system-on-a-chip applications
-
K. Imai, K. Yamaguchi, T. Kudo, N. Kimizuka, and H. Onishi, "CMOS device optimization for system-on-a-chip applications," in IEDM. Tech. Dig., 2000, pp. 455-458.
-
(2000)
IEDM. Tech. Dig.
, pp. 455-458
-
-
Imai, K.1
Yamaguchi, K.2
Kudo, T.3
Kimizuka, N.4
Onishi, H.5
-
6
-
-
0033149162
-
Analog circuit performance and process-scaling
-
A. J. Annema, "Analog circuit performance and process-scaling, " IEEE Trans. Circuits Syst. II, vol. 46, pp. 717-725, 1999.
-
(1999)
IEEE Trans. Circuits Syst. II
, vol.46
, pp. 717-725
-
-
Annema, A.J.1
-
7
-
-
0029723240
-
Analog circuit design in scaled CMOS technology
-
W. Sansen, "Analog circuit design in scaled CMOS technology," in VLSI Symp. Tech. Dig., 1996, pp. 8-11.
-
(1996)
VLSI Symp. Tech. Dig.
, pp. 8-11
-
-
Sansen, W.1
-
8
-
-
0003140671
-
Analog design in deep-sub-micron CMOS
-
K. Bult, "Analog design in deep-sub-micron CMOS," in Proc. ESS-CIRC, 2000, pp. 1-17.
-
(2000)
Proc. ESS-CIRC
, pp. 1-17
-
-
Bult, K.1
-
9
-
-
0031188590
-
CMOS technology for mixed signal ICs
-
M. J. M. Pelgrom and M. Vertregt, "CMOS technology for mixed signal ICs," Solid-State Electron., vol. 41, no. 7, pp. 967-974, 1997.
-
(1997)
Solid-state Electron.
, vol.41
, Issue.7
, pp. 967-974
-
-
Pelgrom, M.J.M.1
Vertregt, M.2
-
10
-
-
0002666776
-
Analog broadband communication circuits in pure digital deep sub-micron CMOS
-
K. Bult, "Analog broadband communication circuits in pure digital deep sub-micron CMOS," in IEEE ISSCC Tech. Dig., 1999, pp. 76-77.
-
(1999)
IEEE ISSCC Tech. Dig.
, pp. 76-77
-
-
Bult, K.1
-
11
-
-
0031120671
-
Potential design and transport property of 0.1-μm MOSFET with asymmetric channel profile
-
Apr.
-
S. Odanaka and A. Hiroki, "Potential design and transport property of 0.1-μm MOSFET with asymmetric channel profile," IEEE Trans. Electron Devices, vol. 44, pp. 595-600, Apr. 1997.
-
(1997)
IEEE Trans. Electron Devices
, vol.44
, pp. 595-600
-
-
Odanaka, S.1
Hiroki, A.2
-
12
-
-
0033281303
-
Channel engineering for high-speed sub-1.0 V power supply deep sub-micron CMOS
-
B. Cheng, A. Inani, V. R. Rao, and J. C. S. Woo, "Channel engineering for high-speed sub-1.0 V power supply deep sub-micron CMOS," in VLSI Symp. Tech. Dig., 1999, pp. 69-70.
-
(1999)
VLSI Symp. Tech. Dig.
, pp. 69-70
-
-
Cheng, B.1
Inani, A.2
Rao, V.R.3
Woo, J.C.S.4
-
13
-
-
0035691874
-
Analog device design for low-power mixed mode applications in sub-micron technology
-
Dec.
-
H. V. Deshpande, B. Cheng, and J. C. S. Woo, "Analog device design for low-power mixed mode applications in sub-micron technology," IEEE Electron Dev. Lett., vol. 22, Dec. 2001.
-
(2001)
IEEE Electron Dev. Lett.
, vol.22
-
-
Deshpande, H.V.1
Cheng, B.2
Woo, J.C.S.3
-
14
-
-
0036610054
-
Optimization and realization of sub-10-nm channel length single halo p-MOSFETs
-
June
-
D. G. Borse, K. N. M. Rani, N. K. Jha, A. N. Chandorkar, J. Vasi, V. R. Rao, B. Cheng, and J. C. S. Woo, "Optimization and realization of sub-10-nm channel length single halo p-MOSFETs," IEEE Trans. Electron Devices, vol. 49, pp. 1077-1078, June 2002.
-
(2002)
IEEE Trans. Electron Devices
, vol.49
, pp. 1077-1078
-
-
Borse, D.G.1
Rani, K.N.M.2
Jha, N.K.3
Chandorkar, A.N.4
Vasi, J.5
Rao, V.R.6
Cheng, B.7
Woo, J.C.S.8
-
15
-
-
0348153060
-
Performance and reliability of single halo deep sub-micron p-MOSFETs for analog applications
-
July
-
N. K. Jha, M. S. Baghini, and V. R. Rao, "Performance and reliability of single halo deep sub-micron p-MOSFETs for analog applications," Proc. IPFA, pp. 35-39, July 2002.
-
(2002)
Proc. IPFA
, pp. 35-39
-
-
Jha, N.K.1
Baghini, M.S.2
Rao, V.R.3
-
16
-
-
0348153070
-
-
Release 6.0
-
ISE-TCAD Manuals, 2000, Release 6.0.
-
(2000)
ISE-TCAD Manuals
-
-
-
17
-
-
0033334509
-
Exploration of velocity overshoot in a high-performance deep sub 100 nm SOI MOSFET with asymmetric channel profile
-
Oct.
-
B. Cheng, V. R. Rao, and J. C. S. Woo, "Exploration of velocity overshoot in a high-performance deep sub 100 nm SOI MOSFET with asymmetric channel profile," IEEE Electron Device Lett., vol. 20, pp. 538-540, Oct. 1999.
-
(1999)
IEEE Electron Device Lett.
, vol.20
, pp. 538-540
-
-
Cheng, B.1
Rao, V.R.2
Woo, J.C.S.3
|