What are the limiting parameters of deep-submicron MOSFETs for high frequency applications?

IEEE Electron Device Letters

Volumn 24, Issue 3, 2003, Pages 189-191

  Dambrine, G ^a   Raynaud, C ^b   Lederer, D ^c   Dehan, M ^c   Rozeaux, O ^d   Vanmackelberg, M ^a   Danneville, F ^a   Lepilliet, S ^a   Raskin, J P ^c  

^a INSTITUT D ELECTRONIQUE   (France)

^b STMICROELECTRONICS   (France)

^c UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

^d CEA LETI   (France)

Author keywords

RF CMOS; RF SOI; Silicon device characterization

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; ELECTRIC CONDUCTANCE; GATES (TRANSISTOR); HIGH ELECTRON MOBILITY TRANSISTORS; OPTIMIZATION; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE STRUCTURES; SILICON ON INSULATOR TECHNOLOGY;

CHANNEL GATE LENGTH; PARASITIC FEEDBACK GATE-TO-DRAIN CAPACITANCE; PHYSICAL CHANNEL LENGTH REDUCTION;

MOSFET DEVICES;

EID: 0037600562     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2003.809525     Document Type: Letter

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