메뉴 건너뛰기




Volumn 15, Issue 11, 2007, Pages 1256-1269

The design of high-performance dynamic asynchronous pipelines: Lookahead style

Author keywords

Asynchronous; Dynamic logic; Elastic pipelining; Gate level pipelines; Latch controllers; Micropipelines; Pipeline processing; Precharge logic

Indexed keywords

ASYNCHRONOUS MACHINERY; CIRCUIT SIMULATION; FLIP FLOP CIRCUITS; PRODUCT DESIGN; THROUGHPUT;

EID: 35448944310     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2007.902205     Document Type: Article
Times cited : (55)

References (43)
  • 3
    • 0032682407 scopus 로고    scopus 로고
    • B. Chappell, 'The fine art of IC design, IEEE Spectrum, 36, no. 7, pp. 30-34, Jul. 1999.
    • B. Chappell, 'The fine art of IC design," IEEE Spectrum, vol. 36, no. 7, pp. 30-34, Jul. 1999.
  • 5
    • 35448960937 scopus 로고    scopus 로고
    • Terabit crossbar switch core for multi-clock-domain SoCs
    • U. Cummings, 'Terabit crossbar switch core for multi-clock-domain SoCs," in Proc. Symp. Rec. Hot Chips, 2003, pp. 102-112.
    • (2003) Proc. Symp. Rec. Hot Chips , pp. 102-112
    • Cummings, U.1
  • 6
    • 0001158270 scopus 로고
    • Investigation into micropipeline latch design styles
    • Jun
    • P. Day and J. V. Woods, "Investigation into micropipeline latch design styles." IEEE Trans. Very Large Scale Integr: (VLSI) Syst., vol. 3, no. 2, pp. 264-272, Jun. 1995.
    • (1995) IEEE Trans. Very Large Scale Integr: (VLSI) Syst , vol.3 , Issue.2 , pp. 264-272
    • Day, P.1    Woods, J.V.2
  • 7
    • 84881252910 scopus 로고    scopus 로고
    • Single-track asynchronous pipeline templates using 1-of-N encoding
    • M. Ferretti and P. A. Beerel, "Single-track asynchronous pipeline templates using 1-of-N encoding," in Proc. Des., Autom. Test Eur: (DATE), 2002, pp. 1008-1015.
    • (2002) Proc. Des., Autom. Test Eur: (DATE) , pp. 1008-1015
    • Ferretti, M.1    Beerel, P.A.2
  • 11
    • 0031273943 scopus 로고    scopus 로고
    • Skew-tolerant domino circuits
    • Nov
    • D. Harris and M. Horowitz, "Skew-tolerant domino circuits," IEEE J. Solid-State Circuits, vol. 32, no. 11, pp. 1702-1711, Nov. 1997.
    • (1997) IEEE J. Solid-State Circuits , vol.32 , Issue.11 , pp. 1702-1711
    • Harris, D.1    Horowitz, M.2
  • 12
    • 77953005154 scopus 로고    scopus 로고
    • VLSI system design using asynchronous wave pipelines: A 0.35 μm CMOS 1.5 GHz elliptic curve public key cryptosystem chip
    • O. Hauck, A. Katoch, and S. A. Huss, "VLSI system design using asynchronous wave pipelines: A 0.35 μm CMOS 1.5 GHz elliptic curve public key cryptosystem chip," in Proc. Int. Symp. Adv. Res. Asynch. Circuits Syst., 2000, pp. 188-197.
    • (2000) Proc. Int. Symp. Adv. Res. Asynch. Circuits Syst , pp. 188-197
    • Hauck, O.1    Katoch, A.2    Huss, S.A.3
  • 13
    • 35448936992 scopus 로고    scopus 로고
    • Online, Available
    • International Technology Roadmap for Semiconductors, "Overall roadmap technology characteristics," 2005. [Online], Available: http://www.itrs.net/Common/2005ITRS/Home2005.htm.
    • (2005) Overall roadmap technology characteristics
  • 15
    • 0033080328 scopus 로고    scopus 로고
    • Modeling and design of asynchronous circuits
    • Feb
    • M. B. Josephs, S. M. Nowick, and C. H. K. van Berkel, "Modeling and design of asynchronous circuits," Proc. IEEE, vol. 87, no. 2, pp. 234-242, Feb. 1999.
    • (1999) Proc. IEEE , vol.87 , Issue.2 , pp. 234-242
    • Josephs, M.B.1    Nowick, S.M.2    van Berkel, C.H.K.3
  • 17
    • 77957958738 scopus 로고    scopus 로고
    • Asynchronous datapath with software-controlled on-chip adaptive voltage scaling for multirate signal processing applications
    • Y. W. Li, G. Patounakis, A. Jose, K. L. Shepard, and S. M. Nowick, "Asynchronous datapath with software-controlled on-chip adaptive voltage scaling for multirate signal processing applications," in Proc. Int. Symp. Asynch. Circuits Syst., 2003, pp. 216-225.
    • (2003) Proc. Int. Symp. Asynch. Circuits Syst , pp. 216-225
    • Li, Y.W.1    Patounakis, G.2    Jose, A.3    Shepard, K.L.4    Nowick, S.M.5
  • 18
    • 35449008228 scopus 로고    scopus 로고
    • A. M. Lines, Pipelined asynchronous circuits, M.S. thesis, Dept. Comput. Sci., California Inst. Technol., Pasadena, 1998.
    • A. M. Lines, "Pipelined asynchronous circuits," M.S. thesis, Dept. Comput. Sci., California Inst. Technol., Pasadena, 1998.
  • 21
    • 0346265964 scopus 로고    scopus 로고
    • A. J. Martin, M. Nyström, and C. G. Wong, 'Three generations of asynchronous microprocessors, IEEE Des. Test Comput., 20, no. 6, pp. 9-17, Nov./Dec. 2003.
    • A. J. Martin, M. Nyström, and C. G. Wong, 'Three generations of asynchronous microprocessors," IEEE Des. Test Comput., vol. 20, no. 6, pp. 9-17, Nov./Dec. 2003.
  • 23
    • 0030387985 scopus 로고    scopus 로고
    • Static timing analysis for self resetting circuits
    • V. Narayanan, B. Chappell, and B. Fleischer, "Static timing analysis for self resetting circuits," in Proc. ICCAD, 1996, pp. 119-126.
    • (1996) Proc. ICCAD , pp. 119-126
    • Narayanan, V.1    Chappell, B.2    Fleischer, B.3
  • 26
    • 0003418582 scopus 로고    scopus 로고
    • Single-rail handshake circuits,
    • Ph.D. dissertation, Dept. Math. Comput. Sci, Eindhoven Univ. Technol, Eindhoven, The Netherlands
    • A. M. G. Peeters, "Single-rail handshake circuits," Ph.D. dissertation, Dept. Math. Comput. Sci., Eindhoven Univ. Technol., Eindhoven, The Netherlands, 1996.
    • (1996)
    • Peeters, A.M.G.1
  • 28
    • 0034431019 scopus 로고    scopus 로고
    • Asynchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz
    • S. Schuster, W. Reohr, P. Cook, D. Heidel, M. Immediato, and K. Jenkins, "Asynchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz," in Proc. ISSCC, 2000, pp. 292-293.
    • (2000) Proc. ISSCC , pp. 292-293
    • Schuster, S.1    Reohr, W.2    Cook, P.3    Heidel, D.4    Immediato, M.5    Jenkins, K.6
  • 29
    • 0001951703 scopus 로고
    • System timing
    • C. A. Mead and L. A. Conway, Eds. Reading, MA: Addison-Wesley, ch. 7
    • C. L. Seitz, "System timing," in Introduction to VLSI Systems, C. A. Mead and L. A. Conway, Eds. Reading, MA: Addison-Wesley, 1980, ch. 7.
    • (1980) Introduction to VLSI Systems
    • Seitz, C.L.1
  • 31
    • 35448967798 scopus 로고    scopus 로고
    • The design of high-throughput asynchronous dynamic pipelines: High-capacity pipelines
    • Nov
    • M. Singh, and S. M. Nowick, "The design of high-throughput asynchronous dynamic pipelines: High-capacity pipelines," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 15, no. 11, pp. XXX-XXX, Nov. 2007.
    • (2007) IEEE Trans. Very Large Scale Integr. (VLSI) Syst , vol.15 , Issue.11
    • Singh, M.1    Nowick, S.M.2
  • 32
    • 77957934332 scopus 로고    scopus 로고
    • High-throughput asynchronous pipelines for fine-grain dynamic datapaths
    • M. Singh and S. M. Nowick, "High-throughput asynchronous pipelines for fine-grain dynamic datapaths," in Proc. Int. Symp. Adv. Res. Asynch. Circuits Syst., 2000, pp. 198-209.
    • (2000) Proc. Int. Symp. Adv. Res. Asynch. Circuits Syst , pp. 198-209
    • Singh, M.1    Nowick, S.M.2
  • 33
    • 77957931942 scopus 로고    scopus 로고
    • An adaptively-pipelined mixed synchronous-asynchronous digital FIR filter chip operating at 1.3 gigahertz
    • M. Singh, J. A. Tierno, A. Rylyakov, S. Rylov, and S. M. Nowick, "An adaptively-pipelined mixed synchronous-asynchronous digital FIR filter chip operating at 1.3 gigahertz," in Proc. Int. Symp. Asynch. Circuits Syst., 2002, pp. 84-95.
    • (2002) Proc. Int. Symp. Asynch. Circuits Syst , pp. 84-95
    • Singh, M.1    Tierno, J.A.2    Rylyakov, A.3    Rylov, S.4    Nowick, S.M.5
  • 37
    • 0024683698 scopus 로고
    • Micropipelines
    • Jun
    • I. E. Sutherland, "Micropipelines," Commun. ACM, vol. 32, no. 6, pp. 720-738, Jun. 1989.
    • (1989) Commun. ACM , vol.32 , Issue.6 , pp. 720-738
    • Sutherland, I.E.1
  • 38
    • 35448934598 scopus 로고    scopus 로고
    • Sun Microsystems, Mountain View, CA, The UltraSPARC IIIi processor architecture overview. Technical whitepaper, 2004 [Online]. Available: http://www.sun.com/processors/whitepapers/US3i_External.pdf
    • Sun Microsystems, Mountain View, CA, "The UltraSPARC IIIi processor architecture overview. Technical whitepaper," 2004 [Online]. Available: http://www.sun.com/processors/whitepapers/US3i_External.pdf
  • 39
    • 0003795268 scopus 로고
    • Self-timed rings and their application to division,
    • Ph.D. dissertation, Dept. Electr. Eng. Comput. Sci, Stanford Univ, Stanford, CA
    • T. E. Williams, "Self-timed rings and their application to division," Ph.D. dissertation, Dept. Electr. Eng. Comput. Sci., Stanford Univ., Stanford, CA, 1991.
    • (1991)
    • Williams, T.E.1
  • 40
    • 0026259615 scopus 로고
    • A zero-overhead self-timed 160 ns 54 b CMOS divider
    • Nov
    • T. E. Williams and M. A. Horowitz, "A zero-overhead self-timed 160 ns 54 b CMOS divider," IEEE J. Solid-State Circuits, vol. 26, no. 11, pp. 1651-1661, Nov. 1991.
    • (1991) IEEE J. Solid-State Circuits , vol.26 , Issue.11 , pp. 1651-1661
    • Williams, T.E.1    Horowitz, M.A.2
  • 42
    • 0030409621 scopus 로고    scopus 로고
    • Clock-delayed domino for adder and combinational logic design
    • G. Yee and C. Sechen, "Clock-delayed domino for adder and combinational logic design," in Proc. ICCD, 1996, pp. 332-337.
    • (1996) Proc. ICCD , pp. 332-337
    • Yee, G.1    Sechen, C.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.