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Volumn , Issue , 2002, Pages 1000-1007

High-speed non-linear asynchronous pipelines

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS PIPELINE; EFFICIENT CONTROL; LINEAR DYNAMICS; MULTIPLE INPUTS; MULTIPLE OUTPUTS; REAL SYSTEMS; SPICE SIMULATIONS; TIMING ANALYSIS;

EID: 84893814503     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2002.998422     Document Type: Conference Paper
Times cited : (23)

References (16)
  • 3
    • 0034431019 scopus 로고    scopus 로고
    • Asynchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz
    • S. Schuster, W. Reohr, P. Cook, D. Heidel, M. Immediato, and K. Jenkins. "Asynchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz," in ISSCC 2000, pp. 292-293.
    • (2000) ISSCC , pp. 292-293
    • Schuster, S.1    Reohr, W.2    Cook, P.3    Heidel, D.4    Immediato, M.5    Jenkins, K.6
  • 7
    • 84961967572 scopus 로고    scopus 로고
    • Fine-grain pipelined asynchronous adders for high-speed DSP applications
    • Orlando, FL, April
    • M. Singh, and S.M. Nowick. "Fine-grain pipelined asynchronous adders for high-speed DSP applications" in Proc. of IEEE Computer Society Annual Workshop on VLSI, Orlando, FL, April 2000, pp. 111-118.
    • (2000) Proc. of IEEE Computer Society Annual Workshop on VLSI , pp. 111-118
    • Singh, M.1    Nowick, S.M.2
  • 8
    • 0035186879 scopus 로고    scopus 로고
    • MOUSETRAP: Ultra-high-speed transition-signaling asynchronous pipelines
    • Austin, TX, September
    • M. Singh, and S.M. Nowick. "MOUSETRAP: Ultra-High-Speed Transition-Signaling Asynchronous Pipelines" in Proc. of Intl. Conf. on Computer Design (ICCD), Austin, TX, September 2001.
    • (2001) Proc. of Intl. Conf. on Computer Design (ICCD)
    • Singh, M.1    Nowick, S.M.2
  • 11
    • 36348979769 scopus 로고
    • M.Sc. thesis, California Institute of Technology, June revised 1998
    • Andrew Matthew Lines. Pipelined Asynchronous Circuits. M.Sc. thesis, California Institute of Technology, June 1995, revised 1998.
    • (1995) Lines Pipelined Asynchronous Circuits
    • Matthew, A.1
  • 12
    • 0001951703 scopus 로고
    • System timing
    • Carver A. Mead and Lynn A. Conway, editors, chapter 7. Addison-Wesley
    • Charles L. Seitz. "System Timing," in Carver A. Mead and Lynn A. Conway, editors, Introduction to VLSI Systems, chapter 7. Addison-Wesley, 1980.
    • (1980) Introduction to VLSI Systems
    • Seitz, C.L.1
  • 15
    • 0028697961 scopus 로고
    • Evaluation of function blocks for asynchronous design
    • Christian D. Nielsen. "Evaluation of Function Blocks for Asynchronous Design," in Proc. of EURODAC, pp. 454-459, 1994.
    • (1994) Proc. of EURODAC , pp. 454-459
    • Nielsen, C.D.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.