Doubly-latched asynchronous pipeline

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1997, Pages 706-711

  Kol, Rakefet ^a   Ginosar, Ran ^a  

^a TECHNION ISRAEL INSTITUTE OF TECHNOLOGY   (Israel)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; FLIP FLOP CIRCUITS; PIPELINE PROCESSING SYSTEMS; SHIFT REGISTERS;

DOUBLY LATCHED ASYNCHRONOUS PIPELINE (DLAP);

ASYNCHRONOUS SEQUENTIAL LOGIC;

EID: 0031384827     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)