-
2
-
-
0345272496
-
Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling
-
G. Semeraro, G. Magklis, R. Balasubramonian, D. H. Albonesi, S. Dwaradasas, and M. L. Scott. Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling. In Proc. Intl. Symp. on High Performance Computer Architecture, 2002.
-
(2002)
Proc. Intl. Symp. on High Performance Computer Architecture
-
-
Semeraro, G.1
Magklis, G.2
Balasubramonian, R.3
Albonesi, D.H.4
Dwaradasas, S.5
Scott, M.L.6
-
4
-
-
0028710966
-
Low-power operation used self-timed circuits and adaptive scaling of the supply voltage
-
L. S. Nielsen, C. Niessen, J. Sparso, and C. H. van Berkel. Low-power operation used self-timed circuits and adaptive scaling of the supply voltage. IEEE Transactions on VLSI Systems, 2(4):391-397, 1994.
-
(1994)
IEEE Transactions on VLSI Systems
, vol.2
, Issue.4
, pp. 391-397
-
-
Nielsen, L.S.1
Niessen, C.2
Sparso, J.3
Van Berkel, C.H.4
-
6
-
-
0036911921
-
Managing power and performance for system-on-chip designs using voltage islands
-
D. E. Lackey, P. S. Zuchowski, T. R. Bednar, D. W. Stout, S. W. Gould, and J. M. Cohn. Managing power and performance for system-on-chip designs using voltage islands. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pages 195-202, 2002.
-
(2002)
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design
, pp. 195-202
-
-
Lackey, D.E.1
Zuchowski, P.S.2
Bednar, T.R.3
Stout, D.W.4
Gould, S.W.5
Cohn, J.M.6
-
9
-
-
0033114882
-
A fully digital, energy-efficient adaptive power-supply regulator
-
April
-
G.-Y. Wei and M. Horowitz. A fully digital, energy-efficient adaptive power-supply regulator. IEEE Journal Solid-State Circuits, pages 520-528, April 2000.
-
(2000)
IEEE Journal Solid-State Circuits
, pp. 520-528
-
-
Wei, G.-Y.1
Horowitz, M.2
-
10
-
-
0032642496
-
A low-power DSP core-based software radio architecture
-
James E. Gunn, Kenneth S. Barron, and William Ruczczyk. A low-power DSP core-based software radio architecture. IEEE Journal on Selected Areas in Communication, 17(4):574-590, 1999.
-
(1999)
IEEE Journal on Selected Areas in Communication
, vol.17
, Issue.4
, pp. 574-590
-
-
Gunn, J.E.1
Barron, K.S.2
Ruczczyk, W.3
-
11
-
-
0026257568
-
A 2-ns cycle, 3.8 ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture
-
T. I. Chappell, B. A. Chappell, S. E. Schuster, J. W. Allen, S. P. Klepner, R. V. Joshi, and R. L. Franch. A 2-ns cycle, 3.8 ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture. IEEE Journal of Solid-State Circuits, 26(11):1577-1585, 1991.
-
(1991)
IEEE Journal of Solid-State Circuits
, vol.26
, Issue.11
, pp. 1577-1585
-
-
Chappell, T.I.1
Chappell, B.A.2
Schuster, S.E.3
Allen, J.W.4
Klepner, S.P.5
Joshi, R.V.6
Franch, R.L.7
-
12
-
-
0029701814
-
Self resetting logic register and incrementer
-
R. A. Haring, M. S. Milshtein, T. I. Chappell, S. H. Dhong, and B. A. Chappell. Self resetting logic register and incrementer. In Proceedings of the Symposium on VLSI Circuits, pages 18-19, 1996.
-
(1996)
Proceedings of the Symposium on VLSI Circuits
, pp. 18-19
-
-
Haring, R.A.1
Milshtein, M.S.2
Chappell, T.I.3
Dhong, S.H.4
Chappell, B.A.5
-
13
-
-
6644229433
-
A 0.18-μm CMOS IA-32 processor with a 4-GHz integer execution unit
-
DOI 10.1109/4.962281, PII S001892000108218X, 2001 ISSCC: Digital, Memory, and Signal Processing
-
G. Hinton, M. Upton, D.J. Sager, D. Boggs, D.M. Carmean, P. Roussel, T. I. Chappell, T. D. Fletcher, M. S. Milshtein, M. Sprague, S. Samaan, and R. Murray. A 0.18 um CMOS IA-32 processing with a 4-GHz integer execution unit. IEEE Journal Solid-Stale Circuits, 36(11):1617-1627,2001. (Pubitemid 33105925)
-
(2001)
IEEE Journal of Solid-State Circuits
, vol.36
, Issue.11
, pp. 1617-1627
-
-
Hinton, G.1
Upton, M.2
Sager, D.J.3
Boggs, D.4
Carmean, D.M.5
Roussel, P.6
Chappell, T.I.7
Fletcher, T.D.8
Milshtein, M.S.9
Sprague, M.10
Samaan, S.11
Murray, R.12
-
14
-
-
0030717943
-
A 15Kb 1.5 ns access on-chip tag SRAM
-
P. F. Lu, S. P. Kowalcyzk, A. P. Pelella, W. V. Huott, U. Bakhru, J. Rawlins, P. Patel, Y. H. Chan, and K. A. Jenkins. A 15Kb 1.5 ns access on-chip tag SRAM. In Proceedings of International Symposium on VLSI Circuits, pages 208-212, 1997.
-
(1997)
Proceedings of International Symposium on VLSI Circuits
, pp. 208-212
-
-
Lu, P.F.1
Kowalcyzk, S.P.2
Pelella, A.P.3
Huott, W.V.4
Bakhru, U.5
Rawlins, J.6
Patel, P.7
Chan, Y.H.8
Jenkins, K.A.9
-
15
-
-
0026259615
-
A zero-overhead self-timed 160ns 54b cmos divider
-
November
-
T. Williams and Mark Horowitz. A zero-overhead self-timed 160ns 54b cmos divider. IEEE Journal Solid-State Circuits, 26:1651-1661, November 1991.
-
(1991)
IEEE Journal Solid-State Circuits
, vol.26
, pp. 1651-1661
-
-
Williams, T.1
Horowitz, M.2
-
16
-
-
77957931942
-
An adaptively-pipelined mixed synchronous-asynchronous digital FIR filter chip operating at 1.3GHz
-
M. Singh, J. A. Tierno, A. Rylyakov, S. Rylov, and S. M. Nowick. An adaptively-pipelined mixed synchronous-asynchronous digital FIR filter chip operating at 1.3GHz. In Proceedings of the IEEE International Symposium on Asynchronous Circuits and Systems, 2002.
-
(2002)
Proceedings of the IEEE International Symposium on Asynchronous Circuits and Systems
-
-
Singh, M.1
Tierno, J.A.2
Rylyakov, A.3
Rylov, S.4
Nowick, S.M.5
-
18
-
-
0033080303
-
Two fifo ring performance experiments
-
February
-
C.E. Molnar, I.W. Jones, W.S. Coates, J.K. Lexau, S.M. Fairbanks, and I.E. Sutherland. Two fifo ring performance experiments. Proceedings of the IEEE, pages 297-307, February 1999.
-
(1999)
Proceedings of the IEEE
, pp. 297-307
-
-
Molnar, C.E.1
Jones, I.W.2
Coates, W.S.3
Lexau, J.K.4
Fairbanks, S.M.5
Sutherland, I.E.6
-
19
-
-
0034431019
-
Asynchronous interlocked pipelined CMOS circuits operating at 3.3-4.5GHz
-
S. Schuster, W. Reohr, P. Cook, D. Heidel, M. Immediato, and K. Jenkins. Asynchronous interlocked pipelined CMOS circuits operating at 3.3-4.5GHz. In Digest Technical Papers, International Solid-State Circuits Conference, pages 292-293, 2000.
-
(2000)
Digest Technical Papers, International Solid-State Circuits Conference
, pp. 292-293
-
-
Schuster, S.1
Reohr, W.2
Cook, P.3
Heidel, D.4
Immediato, M.5
Jenkins, K.6
-
21
-
-
0032136258
-
A replica technique for wordline and sense control in low-power SRAMs
-
B. S. Amruter and M. A. Horowitz. A replica technique for wordline and sense control in low-power SRAMs. IEEE Journal Solid-State Circuits, 33(8): 1208-1219, 1998.
-
(1998)
IEEE Journal Solid-State Circuits
, vol.33
, Issue.8
, pp. 1208-1219
-
-
Amruter, B.S.1
Horowitz, M.A.2
-
22
-
-
0029727772
-
Automatic synthesis of extended burst-mode circuits using generalized c-elements
-
K. Y. Yun. Automatic synthesis of extended burst-mode circuits using generalized c-elements. In Proceedings of the European Design Automation Conference, pages 290-295, 1996.
-
(1996)
Proceedings of the European Design Automation Conference
, pp. 290-295
-
-
Yun, K.Y.1
-
23
-
-
0036113496
-
A 1.3 GSample/s 10-tap full-rate variablelatency self-timed FIR with clocked interfaces
-
J. Tiemo, A. Rylyakov, S. Rylov, M. Singh, S. M. Nowick, M. Immediato, and S. Gowda. A 1.3 GSample/s 10-tap full-rate variablelatency self-timed FIR with clocked interfaces. In Digest Technical Papers, International Solid-State Circuits Conference, 2002.
-
(2002)
Digest Technical Papers, International Solid-State Circuits Conference
-
-
Tiemo, J.1
Rylyakov, A.2
Rylov, S.3
Singh, M.4
Nowick, S.M.5
Immediato, M.6
Gowda, S.7
-
24
-
-
0032022688
-
Automated low-power technique exploiting multiple supply voltages applied to a media processor
-
K. Usami, M. Igarashi, F. Minami, T. Ishikawa, M. Kanzawa, M. Ichida, and K. Nogami. Automated low-power technique exploiting multiple supply voltages applied to a media processor. IEEE Journal Solid-State Circuits, 33(3):463-472, 1998.
-
(1998)
IEEE Journal Solid-State Circuits
, vol.33
, Issue.3
, pp. 463-472
-
-
Usami, K.1
Igarashi, M.2
Minami, F.3
Ishikawa, T.4
Kanzawa, M.5
Ichida, M.6
Nogami, K.7
-
25
-
-
0032123754
-
Embedded 5v-to-3.3v voltage regulator for supplying digital IC's in 3.3v CMOS technology
-
July
-
G. W. den Besten and B. Nauta. Embedded 5v-to-3.3v voltage regulator for supplying digital IC's in 3.3v CMOS technology. IEEE Journal of Solid-State Circuits. 33(7), July 1998.
-
(1998)
IEEE Journal of Solid-State Circuits
, vol.33
, Issue.7
-
-
Den Besten, G.W.1
Nauta, B.2
-
32
-
-
0036916414
-
Methods for true power minimizatioin
-
Robert W. Brodersen, Mark A. Horowitz, Dejan Markovic, and Vladimir Stojanovic Borivoje Nikolic. Methods for true power minimizatioin. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pages 35-42, 2002.
-
(2002)
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design
, pp. 35-42
-
-
Brodersen, R.W.1
Horowitz, M.A.2
Markovic, D.3
Stojanovic, V.4
Nikolic, B.5
-
33
-
-
0036953966
-
Unified methodology for resolving power-performance tradeoffs at the microarchitectural and circuit levels
-
Victor Zyuban and Philip Strenski. Unified methodology for resolving power-performance tradeoffs at the microarchitectural and circuit levels. In Intl. Symp. on Low Power Electronics and Design, pages 166-171,2002.
-
(2002)
Intl. Symp. on Low Power Electronics and Design
, pp. 166-171
-
-
Zyuban, V.1
Strenski, P.2
|