Understanding scheduling replay schemes

IEEE High-Performance Computer Architecture Symposium Proceedings

Volumn 10, Issue , 2004, Pages 198-209

  Kim, Ilhyun ^a   Lipasti, Mikko H ^a  

^a UNIVERSITY OF WISCONSIN MADISON   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA DEPENDENCE; INFORMATION PROPAGATION LOOP; TOKEN BASED SELECTIVE REPLAY;

ALGORITHMS; CACHE MEMORY; COMPUTATIONAL COMPLEXITY; FORMAL LOGIC; PARALLEL PROCESSING SYSTEMS; PROGRAM PROCESSORS;

MICROPROCESSOR CHIPS;

EID: 2342535676     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (22)

1. D. C. Burger and T. M. Austin, The Simplescalar tool set, version 2.0, Technical Report CS-TR-97-1342, University of Wisconsin, Madison, June 1997.
2. Compaq Computer Corporation, Alpha 21264 microprocessor hardware reference manual, July 1999.
3. G. Hinton et al., The microarchitecture of the Pentium 4 processor, Intel Technology Journal Q1, 2001.
4. A. KleinOsowski, J. Flynn, N. Meares and D. J. Lilja, Adapting the SPEC2000 benchmarks suite for simulation-based computer architecture research, Workshop on Workload Characterization in International Conference on Computer Design, 2000.
5. J. Stark, M. Brown and Y. Patt, On pipelining dynamic instruction scheduling logic, in Proc. of 33rd International Symposium on Microarchitecture, 2000.
6. I. Kim and M. H. Lipasti, Macro-op scheduling: relaxing scheduling loop constraints, in Proc. of 36th International Symposium on Microarchitecture, 2003.
7. R. M. Tomasulo, An Efficient Algorithm for Exploiting Multiple Arithmetic Units, IBM Journal, Vol. 11, pp. 25-33, 1967.
8. A. Yoaz, M. Erez, R. Ronen and S. Jourdan, Speculation techniques for improving load related instruction scheduling, in Proc. of 26th International Symposium on Computer Architecture, 1999.
9. Y. T. Sazeides, An analysis of value predictability and its application to a superscalar processor, Ph.D thesis at University of Wisconsin-Madison, 1999
10. M. H. Lipasti, C. B. Wilkerson and J. P. Shen, Value locality and load value prediction, in Proc. of Architectural Support for Programming Languages and Operating Systems, 1996.
11. M. H. Lipasti and J. P. Shen, Exceeding the dataflow limit via value prediction, in Proc. of 29th International Symposium on Microarchitecture, 1996.
12. A. Moshovos and G. S. Sohi, Streamlining interoperation memory communication via data dependence prediction, in Proc. of 30th International Symposium on Microarchitecture, 1997.
13. A. Moshovos and G. S. Sohi, Speculative memory cloaking and bypassing, in Proc. of 32nd International Symposium on Microarchitecture, 1999.
14. H. Akkary and M. A. Driscoll, A dynamic multithreading processor, in Proc. of 31st International Symposium on Microarchitecture, 1998.
15. T. Austin and G. Tyson, Improving the accuracy and performance of memory communication through renaming, in Proc. of 30th International Symposium on Microarchitecture, 1997.
16. G. Chrysos and J. Emer, Memory dependence prediction using store sets, in Proc. of 25th International Symposium on Computer Architecture, 1998.
17. A. R. Lebeck, J. Koppanalil, T. Li, J. Patwardhan and E. Rotenberg, A large, fast instruction window for tolerating cache misses, in Proc. of 29th International Symposium on Computer Architecture, 2002.
18. Intel Corporation, Pentium Pro family developers manual, Intel corporation, 1996
19. E. Morancho, J. M. Llaberia and A.Olive, Recovery Mechanism for Latency Misprediction, in Proc. of International Conference on Parallel Architectures and Compilation Techniques, 2001.
20. United States Patent #6,212,626, Computer processor having a checker, Amit A. Merchant and David J. Sager, assigned to Intel Corporation, issued April 3, 2001.
21. J. P. Shen and M. H. Lipasti, Modern Processor Design: Fundamentals of superscalar processors, beta edition, pp. 400-402, McGraw-Hill, 2002.
22. Y. T. Sazeides, Modeling value speculation, in Proc. of International Symposium on High-performance Computer Architecture, 2002.