Kilo-instruction processors: Overcoming the memory wall

IEEE Micro

Volumn 25, Issue 3, 2005, Pages 48-57

  Cristal, Adrián ^a   Santana, Oliverio J ^a   Cazorla, Francisco ^a   Galluzzi, Marco ^a   Ramírez, Tanausú ^a   Pericàs, Miquel ^a   Valero, Mateo ^a  

^a BARCELONA SUPERCOMPUTING CENTER   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; CACHE MEMORY; COMPUTER ARCHITECTURE; DATA STORAGE EQUIPMENT; DESIGN; PERFORMANCE; QUEUEING THEORY; RESOURCE ALLOCATION; SUPERVISORY AND EXECUTIVE PROGRAMS;

IN-FLIGHT INSTRUCTIONS; KILO-INSTRUCTION PROCESSORS; MEMORY WALL; PROCESSOR DESIGN; REORDER BUFFER (ROB); RESOURCE REQUIREMENTS; SUPERSCALAR PROCESSOR;

MICROPROCESSOR CHIPS;

EID: 22944446075     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2005.53     Document Type: Article

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