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Volumn , Issue , 2005, Pages 159-170

Scalable store-load forwarding via store queue index prediction

Author keywords

[No Author keywords available]

Indexed keywords

DATA CACHE; INDEX PREDICTION; LARGE WINDOW PROCESSORS; STORE QUEUE (SQ);

EID: 33749383494     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2005.29     Document Type: Conference Paper
Times cited : (44)

References (22)
  • 1
    • 27544505388 scopus 로고    scopus 로고
    • Decomposing the load-store queue by function for power reduction and scalability
    • Oct.
    • L. Baugh and C. Zilles. "Decomposing the Load-Store Queue by Function for Power Reduction and Scalability." In 2004 IBM P=AC∧2 Conference, Oct. 2004.
    • (2004) 2004 IBM P=AC∧2 Conference
    • Baugh, L.1    Zilles, C.2
  • 4
    • 0007997616 scopus 로고    scopus 로고
    • ARB: A hardware mechanism for dynamic reordering of memory references
    • May
    • M. Franklin and G. Sohi. "ARB: A Hardware Mechanism for Dynamic Reordering of Memory References." IEEE Transactions on Computers, May 1996.
    • (1996) IEEE Transactions on Computers
    • Franklin, M.1    Sohi, G.2
  • 7
    • 0032639289 scopus 로고    scopus 로고
    • The alpha 21264 microprocessor
    • Mar./Apr.
    • R. Kessler. "The Alpha 21264 Microprocessor." IEEE Micro, 19(2), Mar./Apr. 1999.
    • (1999) IEEE Micro , vol.19 , Issue.2
    • Kessler, R.1
  • 12
    • 0033357302 scopus 로고    scopus 로고
    • Dynamic memory disambiguation in the presence of out-of-order store issuing
    • Nov.
    • S. Onder and R. Gupta. "Dynamic Memory Disambiguation in the Presence of Out-of-Order Store Issuing." In Proc. 32nd International Symposium on Microarchitecture, pages 170-176, Nov. 1999.
    • (1999) Proc. 32nd International Symposium on Microarchitecture , pp. 170-176
    • Onder, S.1    Gupta, R.2
  • 15
    • 33646019207 scopus 로고    scopus 로고
    • A high bandwidth low latency load/store unit for single- And multi- threaded processors
    • University of Pennsylvania, Jun.
    • A. Roth. "A High Bandwidth Low Latency Load/Store Unit for Single- and Multi- Threaded Processors." Technical Report MSCIS-04-09, University of Pennsylvania, Jun. 2004.
    • (2004) Technical Report , vol.MSCIS-04-09
  • 16
    • 27544514377 scopus 로고    scopus 로고
    • Store Vulnerability Window (SVW): Re-execution filtering for enhanced load optimization
    • Jun.
    • A. Roth. "Store Vulnerability Window (SVW): Re-Execution Filtering for Enhanced Load Optimization." In Proc. 32nd International Symposium on Computer Architecture, pages 458-468, Jun. 2005.
    • (2005) Proc. 32nd International Symposium on Computer Architecture , pp. 458-468
    • Roth, A.1
  • 18
    • 0003450887 scopus 로고    scopus 로고
    • CACTI 3.0: An integrated cache timing, power, and area model
    • COMPAQ Western Research Laboratory
    • P. Shivakumar and N. Jouppi. "CACTI 3.0: An Integrated Cache Timing, Power, and Area Model." Technical report, COMPAQ Western Research Laboratory, 2001.
    • (2001) Technical Report
    • Shivakumar, P.1    Jouppi, N.2
  • 21
    • 0031356687 scopus 로고    scopus 로고
    • Improving the accuracy and performance of memory communication through renaming
    • Dec.
    • G. Tyson and T. Austin. "Improving the Accuracy and Performance of Memory Communication Through Renaming." In Proc. 30th International Symposium on Microarchitecture, pages 218-227, Dec. 1997.
    • (1997) Proc. 30th International Symposium on Microarchitecture , pp. 218-227
    • Tyson, G.1    Austin, T.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.