Design and implementation of the TRIPS primary memory system

IEEE International Conference on Computer Design, ICCD 2006

Volumn , Issue , 2006, Pages 470-476

  Sethumadhavan, Simha ^a   McDonald, Robert ^a   Desikan, Rajagopalan ^b   Burger, Doug ^a   Keckler, Stephen W ^a  

^a University of Texas at Austin   (United States)

^b The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE LINES; CACHE MISSES; COMPUTER DESIGNS; DESIGN DECISIONS; DESIGN EXPERIENCE; DETAILED DESIGN; FLIGHT LOADS; INTERNATIONAL CONFERENCES; MEMORY SYSTEMS; MICRO ARCHITECTURES; PRIMARY MEMORY;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ION BEAMS;

CHLORINE COMPOUNDS;

EID: 49749127669     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2006.4380858     Document Type: Conference Paper

References (10)

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9. Intel Architecture 32 Family Developer's Manual, Volume 3, Appendix A.2. Intel, 2001.
10. S. Sethumadhavan, D. Burger, and S. W. Keckler, "Partition the Banks, not the functionality, of Large-Window Load-Store Queues," Department of Computer Sciences, The University of Texas at Austin, Tech. Rep. TR-06-39, 2006.