Memory bank predictors

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn 2005, Issue , 2005, Pages 666-668

  Bieschewski, Stefan ^a   Parcerisa, Joan Manuel ^a   González, Antonio ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

Clustered microarchitectures; Memory bank prediction

Indexed keywords

BANDWIDTH; COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; COST EFFECTIVENESS; MICROPROCESSOR CHIPS; PROGRAM PROCESSORS;

CLUSTERED MICROARCHITECTURES; MEMORY BANK PREDICTIONS; MICROARCHITECTURES; SUPERSCALAR PROCESSORS;

BUFFER STORAGE;

EID: 33748546600     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2005.73     Document Type: Conference Paper

References (11)

1. V. Agarwal, et. al. "Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures." ISCA-27, 2000.
2. R. Balasubramonian, et. al. "Microarchitectural Trade-offs in the Design of a Scalable Clustered Microprocessor," Technical Report, University of Rochester, 2003.
3. St. Bieschewski, el. al. "Memory Bank Predictors," Technical Report, Universitat Politècnica de Catalunya, 2005.
4. D. Burger, et. al. "Evaluating Future Microprocessors: The SimpleScalar Tool Set," Tech. Report CS-TR-96-1308, University of Wisconsin-Madison, 1996.
5. B. Goeman, et. al. "Differential FCM: Increasing Value Prediction Accuracy by Improving Table Usage Efficiency," HPCA-01, 2001.
6. H. Neefs, et. al. "A Technique for High Bandwidth and Deterministic Low Latency Load/Store Access to Multiple Cache Banks," HPCA-00, 2000.
7. J. M. Parcerisa, "Design of Clustered Superscalar Microarchitectures", Ph.D. Thesis, Universitat Politècnica de Catalunya, 2004.
8. P. Racunas and Y. N. Patt, "Partitioned first-level cache design for clustered microarchitectures," ICS-03, 2003.
9. Y. Sazeides, and J. E. Smith, "Implementations of Context Based Value Predictors," Technical Report, ECE-97-8, University of Wisconsin-Madison, 1997.
10. A. Yoaz, et. al. "Speculation Techniques for Improving Load Related Instruction Scheduling," ISCA-26, 1999.
11. V. V. Zyuban, P. M. Kogge, "Inherently Lower-Power High-Performance Superscalar Architectures", IEEE Transactions on Computers, March, 2001, Vol. 50, No. 3.