Tradeoffs in power-efficient issue queue design

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 2002, Pages 184-189

  Buyuktosunoglu, Alper ^a   Albonesi, David H ^a   Bose, Pradip ^b   Cook, Peter W ^b   Schuster, Stanley E ^b  

^a University of Rochester   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Adaptation; Banking; Compacting; Issue queue; Low power; Microarchitecture; Non compacting

Indexed keywords

COMPUTER SIMULATION; ELECTRIC POWER SUPPLIES TO APPARATUS; ENERGY CONSERVATION; ENERGY UTILIZATION; INTEGER PROGRAMMING; MICROPROCESSOR CHIPS; OPTIMIZATION;

ADAPTATION; BANKING; COMPACTING; ISSUE QUEUE DESIGN; LOW-POWER; MICROARCHITECTURE; NON-COMPACTING;

MICROCOMPUTERS;

EID: 0036949555     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/lpe.2002.146734     Document Type: Conference Paper

References (11)

1. P. Bose, D. Brooks, A. Buyuktosunoglu, P. Cook, K. Das, P. Emma, M. Gschwind, H. Jacobson, T. Karkhanis, S. Schuster, J . Smith, V. Srinivasan, V. Zyuban, D. Albonesi, S. Dwarkadas. Early-Stage Definition of LPX: A Low Power Issue-Execute Processor Prototype. PACS-02 workshop, HPCA-8, 2002.
2. A. Buyuktosunoglu, S. Schuster, D. Brooks, P. Bose, P. Cook, D. Albonesi. An Adaptive Issue Queue for Reduced Power at High-Performance. Springer-Verlag Lecture Notes in Computer Science Vol. 2008: 25-40, November 2000.
3. G. Kucuk, K. Ghose, D. Ponomarev, P. Kogge. Energy-Efficient Instruction Dispatch Buffer Design for Superscalar Processors. ISLPED-01, 2001.
4. J. Farrell, T. Fischer. Issue Logic for a 600-MHz Out-of-Order Execution Microprocessor. JSSC, 33(5):707-712, May 1998.
5. D. Folegnani, A. Gonzalez. Energy-Effective Issue Logic. ISCA-28, 2001.
6. P. Jordan, B. Konigsburg, H. Le, S. White. Data Processing System and Method for Using an Unique Identifier to Maintain an Age Relationship Between Executing Instructions. IBM Corporation, U.S. patent 5805849, 1997.
7. J. Leenstra, J. Pille, A. Mueller, W. Sauer, R. Sautter, D. Wendel. A 1.8GHz Instruction Window Buffer. ISSCC-01, 2001.
8. H. Miyatake, M. Tanaka, Y. Mori. A Design for High-Speed Low-Power CMOS Fully Parallel Content-Addressable Memory Macros. JSSC, 36(6): 956-968, June 2001.
9. S. Palacharla, N. Jouppi, J. Smith. Complexity-Effective Superscalar Processors. ISCA-24, 1997.
10. J. Tendler, J. Dodson, J. Fields, H. Le, B. Sinharoy. POWER4 System Microarchitecture. IBM J. Research and Development, 46(1):5-27, 2002.
11. K. Wilcox, S. Manne. Alpha Processors: A History of Power Issues and a Look to the Future. Cool Chips Tutorial, MICRO-32, 1999.