Address-indexed memory disambiguation and store-to-load forwarding

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2005, Pages 171-182

  Stone, Sam S ^a   Woley, Kevin M ^a   Frank, Matthew I ^a  

^a University of Illinois at Urbana Champaign   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LOAD/STORE QUEUE (LSQ); MEMORY DISAMBIGUATION TABLE (MDT); STORE-FORWARDING CACHE (SFC);

COMPUTATIONAL COMPLEXITY; COMPUTER AIDED MANUFACTURING; ENERGY UTILIZATION; PROGRAM PROCESSORS; SCHEDULING;

DATA STORAGE EQUIPMENT;

EID: 33749388925     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2005.10     Document Type: Conference Paper

References (26)

1. H. Akkary and K. Chow. Processor having multiple program counters and trace buffers outside an execution pipeline, 2001. U.S. Patent Number 6,182,210.
2. H. Akkary, R. Rajwar, and S. T. Srinivasan. Checkpoint processing and recovery: Towards scalable large instruction window processors. In MICRO 36, page 423, 2003.
3. P. A. Bernstein and N. Goodman. Timestamp-based algorithms for concurrency control in distributed database systems. In Proceedings of the Sixth International Conference on Very Large Data Bases, pages 285-300, Montreal, Canada, Oct. 1980.
4. H. W. Cain and M. H. Lipasti. Memory ordering: A value-based approach. In ISCA-31, pages 90-101, 2004.
5. G. Z. Chrysos and J. S. Emer. Memory dependence prediction using store sets. In 25th International Symposium on Computer Architecture (ISCA-25), pages 142-153, Barcelona, Spain, June 1998.
6. K. A. Feiste, B. J. Ronchetti, and D. J. Shippy. System for store forwarding assigning load and store instructions to groups and reorder queues to keep track of program order, 2002. U.S. Patent Number 6,349,382.
7. M. Franklin. Multi-version caches for Multiscalar processors. In Proceedings of the First International Conference on High Performance Computing (HiPC), 1995.
8. M. Franklin and G. S. Sohi. The expandable split window paradigm for exploiting fine-grain parallelism. In 19th International Symposium on Computer Architecture (ISCA-19), pages 58-67, Gold Coast, Australia, May 1992.
9. M. Franklin and G. S. Sohi. ARB: A hardware mechanism for dynamic reordering of memory references. IEEE Trans. Comput., 45(5):552-571, May 1996.
10. D. M. Gallagher, W. Y. Chen, S. A. Mahlke, J. C. Gyllenhaal, and W. mei W. Hwu. Dynamic memory disambiguation using the memory conflict buffer. In Proceedings of the 6th International. Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pages 183-193, San Jose, California, Oct. 1994.
11. A. Gandhi, H. Akkary, R. Rajwar, S. T. Srinivasan, and K. Lai. Scalable load and store processing in latency tolerant processors. In ISCA 32, pages 446-457, 2005.
12. K. Gharachorloo, A. Gupta, and J. Hennessy. Two techniques to enhance the performance of memory consistency models. In Proceedings of the 1991 International Conference on Parallel Processing, 1991.
13. S. Jourdan, R. Ronen, M. Bekerman, B. Shomar, and A. Yoaz. A novel renaming scheme to exploit value temporal locality through physical register reuse and unification. In MICRO-31, pages 216-225, 1998.
14. T. Knight. An architecture for mostly functional languages. In Proceedings of the ACM Conference on Lisp and Functional Programming, pages 88-93, Aug. 1986.
15. D. Leibholz and R. Razdan. The Alpha 21264: A 500 MHz out-of-order execution microprocessor. In IEEE COMPCON 42, 1997.
16. A. Moshovos, S. E. Breach, T. N. Vijaykumar, and G. S. Sohi. Dynamic speculation and synchronization of data dependences. In ISCA-24, pages 181-193, 1997.
17. A. Moshovos and G. S. Sohi. Streamlining inter-operation memory communication via data dependence prediction. In MICRO-30, 1997.
18. S. Onder and R. Gupta. Dynamic memory disambiguation in the presence of out-of-order store issuing. In MICRO-32, pages 170-176, 1999.
19. I. Park, C. L. Ooi, and T. N. Vijaykumar. Reducing design complexity of the load/store queue. In MICRO 36, pages 411-422, 2003.
20. D. P. Reed. Implementing atomic actions on decentralized data. ACM Trans. Comput. Syst., 1(1):3-23, Feb. 1983.
21. A. Roth. Store vulnerability window (SVW): Re-execution filtering for enhanced load optimization. In ISCA 32, pages 458-468, 2005.
22. S. Sethumadhavan, R. Desikan, D. Burger, C. R. Moore, and S. W. Keckler. Scalable hardware memory disambiguation for high ilp processors. In MICRO 36, pages 399-410, 2003.
23. G. S. Sohi, S. E. Breach, and T. N. Vijaykumar. Multiscalar processors. In 22nd International Symposium on Computer Architecture, pages 414-425, Santa Margherita Ligure, Italy, June 1995.
24. E. F. Torres, P. Ibanez, V. Vinals, and J. M. Llaberia. Store buffer design in first-level multibanked data caches. In ISCA 32, pages 469-480, 2005.
25. G. S. Tyson and T. M. Austin. Improving the accuracy and performance of memory communication through renaming. In MICRO-30, 1997.
26. K. C. Yeager. The MIPS R10000 superscalar microprocessor. IEEE Micro, 16(2):28-40, 1996.