Built-In Redundancy Analysis for Memory Yield Improvement

IEEE Transactions on Reliability

Volumn 52, Issue 4, 2003, Pages 386-399

  Huang, Chih Tsun ^a   Wu, Chi Feng ^a   Li, Jin Fu ^b   Wu, Cheng Wen ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^b NATIONAL CENTRAL UNIVERSITY   (Taiwan)

Author keywords

Built in self diagnosis; Built in self test; DRAM; Embedded memory; Memory testing; Redundancy analysis; SRAM; Yield improvement

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; CONTROL SYSTEMS; ELECTRONIC EQUIPMENT TESTING; EMBEDDED SYSTEMS; MICROPROCESSOR CHIPS; OPTIMIZATION; REDUNDANCY; STATIC RANDOM ACCESS STORAGE; VLSI CIRCUITS;

BUILT-IN SELF-DIAGNOSIS; BUILT-IN SELF-TEST; EMBEDDED MEMORY; MEMORY TESTING; MEMORY YIELD IMPROVEMENTS; REDUNDANCY ANALYSIS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0742290127     PISSN: 00189529     EISSN: None     Source Type: Journal    
DOI: 10.1109/TR.2003.821925     Document Type: Article

References (35)

1. M. Lin, Ed., "1997 Semiconductor Industry Annual Report," (in Chinese), Industrial Technology Research Institute (ITRI), Hsinchu, Taiwan, ITIS project report, 1997.
2. G. E. Moore, "Progress in digital integrated electronics," in Proc. IEEE IEDM, 1975. pp. 11-13.
3. R. P. Cenker, D. G. Clemons, W. P. Huber, J. P. Petrizzi, F. J. Procyk, and G. M. Trout, "A fault-tolerant 64 k dynamic random-access memory, " IEEE Trans. Electron Devices, vol. 26, pp. 853-860, June 1979.
4. R. T. Smith, J. D. Chipala, J. F. M. Bindels, R. G. Nelson, F. H. Fischer, and T. F. Mantz, "Laser programmable redundancy and yield improvement in a 64 k DRAM," IEEE J. Solid-State Circuits, vol. 16, pp. 506-514, Oct. 1981.
5. C. A. Benevit, J. M. Cassard, K. J. Dimmler, A. C. Dumbri, M. G. Mound, F. J. Procyk, W. Rosenzweig, and A. W. Yanof, "A 256 k dynamic random-access memory," IEEE J. Solid-State Circuits, vol. 17, pp. 857-862, Oct. 1982.
6. C.-T. Huang, J.-R. Huang, C.-F. Wu, C.-W. Wu, and T.-Y. Chang, "A programmable BIST core for embedded DRAM," IEEE Design & Test of Computers, vol. 16, pp. 59-70, Jan-Mar. 1999.
7. "Semiconductor industry association," in International Technology Roadmap for Semiconductors (ITRS), Dec. 2000.
8. K. K. Saluja, S. H. Sng, and K. Kinoshita, "Built-in self-testing RAM: A practical alternative," IEEE Design & Test of Computers, vol. 4, pp. 42-51, Feb. 1987.
9. M. Franklin and K. K. Saluja, "Built-in self-testing of random-access memories," IEEE Computer, pp. 45-56, Oct. 1990.
10. B. Nadeau-Dostie, A. Silburt, and V. K. Agarwal, "Serial interface for embedded-memory testing," IEEE Design & Test of Computers, vol. 7, pp. 52-63, Apr. 1990.
11. P. Camurati, P. Prinetto, M. S. Reorda, S. Barbagallo, A. Burri, and D. Medina, "Industrial BIST of embedded RAMs," IEEE Design & Test of Computers, vol. 12, pp. 86-95, 1995.
12. S. Tanoi, Y. Tokunaga, T. Tanabe, K. Takahashi, A. Okada, M. Itoh, Y. Nagatomo, Y. Ohtsuki, and M. Uesugi, "On-wafer BIST of a 200-Gb/s failed-bit search for 1-Gb DRAM," IEEE J. Solid-State Circuits, vol. 32, pp. 1735-1742. Nov. 1997.
13. J. Dreibelbis, J. Barth, H. Kalter, and R. Kho, "Processor-based built-in self-test for embedded DRAM," IEEE J. Solid-State Circuits, pp. 1731-1740, Nov. 1998.
14. R. P. Treuer and V. K. Agarwal, "Built-in self-diagnosis for repairable embedded RAMs," IEEE Design & Test of Computers, vol. 10, pp. 24-33, June 1993.
15. C.-W. Wang, C.-F. Wu, J.-F. Li, C.-W. Wu, T. Teng, K. Chiu, and H.-P. Lin, "A built-in self-test and self-diagnosis scheme for embedded SRAM," in Proc. Ninth IEEE Asian Test Symp. (ATS), Taipei, Dec. 2000, pp. 45-50.
16. P. Mazumder and J. S. Yih, "A novel built-in self-repair approach to VLSI memory yield enhancement," in Proc. Int. Test Conf. (ITC), 1990, pp. 833-841.
17. A. Tanabe, T. Takeshima, H. Koike, Y. Aimoto, M. Takada, T. Ishijima, N. Kasai, H. Hada, K. Shibahara, T. Kunio, T. Tanigawa, T. Saeki, M. Sakao, H. Miyamoto, H. Nozue, S. Ohya, T. Murotani, K. Koyama, and T. Okuda, "A 30-ns 64-Mb DRAM with built-in self-test and self-repair function," IEEE J. Solid-State Circuits, vol. 27, pp. 1525-1533, Nov. 1992.
18. T. Chen and G. Sunada, "Design of a self-testing and self-repairing structure for highly hierarchical ultra-large capacity memory chips," IEEE Tram. VLSI Systems, vol. 1, pp. 88-97, June 1993.
19. P. Mazumder and Y.-S. Jih, "A new built-in self-repair approach to VLSI memory yield enhancement by using neural-type circuits," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 12, pp. 124-136, Jan. 1993.
20. I. Kim, Y. Zorian, G. Komoriya, H. Pham, F. P. Higgins, and J. L. Lweandowski, "Built in self repair for embedded high density SRAM," in Proc. Int. Test Conf. (ITC), Oct. 1998, pp. 1112-1119.
21. D. K. Bhavsar, "An algorithm for row-column self-repair of RAMs and its implementation in the alpha 21 264," in Proc. Int. Test Conf. (ITC), 1999, pp. 311-318.
22. N. Park and E. Lombardi, "Repair of memory arrays by cutting," in Proc. IEEE Int. Workshop on Memory Technology, Design and Testing (MTDT), San Jose, Aug. 1998, pp. 124-130.
23. S.-K. Lu and C.-H. Hsu, "Built-in self-repair for divided word line memory," in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), 2001, pp. 13-16.
24. T. Kawagoe, J. Ohtani, M. Niiro, T. Ooishi, M. Hamada, and H. Hidaka, "A built-in self-repair analyzer (CRESTA) for embedded DRAMs," in Proc. Int. Test Conf. (ITC), 2000, pp. 567-574.
25. J. Ohtani, T. Ooishi, T. Kawagoe, M. Niiro, M. Maruta, and H. Hidaka, "A shared built-in self-repair analysis for multiple embedded memories," in Proc. IEEE Custom Integrated Circuits Conf. (CICC), vol. 4. 2001, pp. 187-190.
26. W.-K. Huang, Y.-N. Shen, and F. Lombardi, "New approaches for the repair of memories with redundancy by row/column deletion for yield enhancement," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 9, pp. 323-328, Mar. 1990.
27. M. Tarr, D. Boudreau, and R. Murphy, "Defect analysis system speeds test and repair of redundant memories," Electronics, pp. 175-179, Jan. 1984.
28. J. R. Day, "A fault-driven, comprehensive redundancy algorithm," IEEE Design & Test of Computers, vol. 2, pp. 35-44, June 1985.
29. S.-Y. Kuo and W. K. Fuchs,"Efficient spare allocation in reconfigurable arrays," IEEE Design & Test of Computers, vol. 4, pp. 24-31, Feb. 1987.
30. C.-L. Wey and F. Lombardi, "On the repair of redundant RAMs," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 6, pp. 222-231, Mar. 1987.
31. R. W. Haddad, A. T. Dahbura, and A. B. Sharma, "Increased throughput for the testing and repair of RAMs with redundancy," IEEE Trans. Computers, vol. 40. pp. 154-166, Feb. 1991.
32. C. H. Stapper, A. N. McLaren, and M. Dreckmann, "Yield model for productivity optimization of VLSI memory chips with redundancy and partially good product," IBM J. Research and Development, vol. 24, pp. 398-409, May 1980.
33. M. Choi and N. Park, "Dynamic yield analysis and enhancement of FPGA reconfigurable memory system," in Proc. 18th IEEE Instrumentation and Measurement Technology Conf. (IMTC), vol. 1, Budapest, Hungary, May 2001, pp. 386-391.
34. M. Choi, N. Park, F. Meyer, F. Lombardi, and V. Piuri, "Reliability measurement of fault-tolerant onboard memory system under fault clustering," in Proc. 19th IEEE Instrumentation and Measurement Technology Conf. (IMTC), vol. 2, Anchorage, AK, May 2002, pp. 1161-1166.
35. C.-F. Wu, C.-T. Huang, C.-W. Wang, K.-L. Cheng, and C.-W. Wu, "Error catch and analysis for semiconductor memories using march tests," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design (ICCAD), San Jose, Nov. 2000, pp. 468-471.