Behavior of NBTI under AC dynamic circuit conditions

IEEE International Reliability Physics Symposium Proceedings

Volumn 2003-January, Issue , 2003, Pages 17-22

  Abadeer, W ^a   Ellis, W ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DYNAMICS; RECONFIGURABLE HARDWARE; THRESHOLD VOLTAGE;

DC OPERATION; DEVICE CURRENTS; DYNAMIC CIRCUITS; FREQUENCY RANGES; GATE OXIDE; POWER FUNCTIONS; SCALED CMOS; STRESS TIME;

INTEGRATED CIRCUITS;

EID: 84955268499     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RELPHY.2003.1197714     Document Type: Conference Paper

References (16)

1. C. Schlunder, R. Brederlow, P. Wieczorek, C. Dahl, J. Holz, M. Rohner, S. Kessel, V. Erold, K. Goser, W. Weber, and R. Thewes, "Trapping Mechanisms in Negative Bias Temperature Stressed p-MOSFETs," Microelectronics Reliability, pp. 821-826, 1999.
2. P. Chaparala, J. Shibley, and P. Lim, "Threshold Voltage Drift in PMOSFETs due to NBTI and HCI," Integrated Reliability Workshop Digest, pp. 95-97, 2000.
3. N. Kimizuka, K. Yamaguchi, K. Imai, T. Iizuka, C. I. Liu, R. C. Keller, and T. Horiuchi, "NBTI Enhancement by Nitrogen Incorporation into Ultrathin Gate Oxide for 0.1m Gate CMOS Generation," Symposium on VLSI Technology Digest, pp. 92093, 2000.
4. H. Aono, E. Murakami, K. Okuyama, K. Makabe, K. Kuroda, K. Watanabe, H. Ozaki, K. Yanagisawa, K. Kubata, and Y. Ohji, "NBTI-Induced hot carrier (HC) Effect: Positive Feedback Mechanism in P-MOSFETs Degradation," Proceedings of the Inter. Rel. Phys. Symp., pp. 282-286, 1997.
5. W. Abadeer, W. Tonti, W. Hansch, and U. Schwalke, "Bias Temperature Reliability of N+ and P+ Polysilicon Gated NMOSFETs and PMOSFETs," Proceedings of the Inter. Rel. Phys. Symp., pp. 147-149, 1993
6. G. La Rosa, F. Guarin, S. Rauch, A. Acovic, J. Lukaitis, and E. Crabe, "NBNTI-Channel Hot carriers Effects in PMOSFETs in Advanced CMOS Technologies," Proceedings of the Inter. Rel. Phys. Symp., pp. 282-286, 1997.
7. Vijay Reddy, Anand T. Krishnan, Andrew Marshall, John Rodriguez, Sreedhar Natarajan, Tim Rost, and Srikanth Krishnan, "Impact of Negative Bias Temperature Instability on Digital Circuit Reliability," Proceedings of the Inter. Rel. Phys. Symp., pp. 248-254, 2002.
8. R. Thewes, R. Brederlow, C. Schlunder, P. Wieczorek, B. Ankele, A. Hesener, J. Holz, S. Kessel, W. Weber, "Evaluation of MOSFET Reliability in Analog Applications," European Solid State Device Research Conf., 2201.
9. B. Zhu, J. S. Suehle, Y. Chen, and J. B. Bernstein, "Negative Bias Temperature Instability of Deep Sub Micron p-MOSFETs Under Pulsed Bias Stress," Proceedings of the Integrated Reliability Workshop (to be published), 2002
10. C. E. Blat, E. H. Nicolian, and E. H. Poindexter, "Mechanism of Negative-Bias-Temperature Instability," Mechanism of Negative-Bias-Temperature Instability, "J. Appl. Phys. vol 69(3), pp. 1712-1720, 1991.
11. F. K. Baker, J. R. Pfiester, T. C. Mele, Hsing-Huang Tseng, P. J. Tobin, J. D. Hayden, C. D. Gunderson, and L. C, Parillo, "The Influence of Fluorine on Threshold Voltage Insatbility in P+ Polysilicon Gated P-Channel MOSFETs," IEDM Technical Digest, pp. 443-446, 1989.
12. H. Ushizaka, and Y. Sato, "The Process Dependence on Positive Bias Temperature Aging Instability of P+ (B) Polysiücon-Gate MOS Devices," IEEE Trans, on Elec. Dev., vol 40, no. 5, pp. 932-937, 1993.
13. H. Iwai, F. Matsuoka, H. Oyamatsu, H. S. Monose, K. Hama, Y. Toyoshima, and H. Hayashida, "BT Reliability for Thin Gate Oxide N+ and P+ Poly MODFETS," Digest of International Semiconductor Interface Specialists Conf., 1989.
14. Y. Hiruta, H. Iwai, F. Matsuoka, K. Hama, K. Maeguchi, and K. Kanzaki, "Interface State Generation Under Long-Term Positive Bias Temperature Stress for a P+ Poly gate MOS Structure, "IEEE Trans, on Elec. Dev., vol. 36, No. 9, pp. 1732-1739, 1989.
15. Shigeo Ogawa, Masakazu Shimaya, and Noboru Shiono, "Interface-Trap Generation at Ultra-thin SiO2 (4-6nm)-Si Interfaces During Negative-Bias Temperature Aging," J. Appl. Phys., 77(3), pp. 1137-1147, 1995.
16. K. Manchanda, "Hot-Electron Trapping and Generic Reliability of P+ Poltsilicon/SiO2/Si Structure for Fine-Line CMOS Technology," Proceedings of the Int. Rel. Phys. Symp., pp. 183-185,1986.