A spatial contrast retina with on-chip calibration for neuromorphic spike-based AER vision systems

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 54, Issue 7, 2007, Pages 1444-1458

  Costas Santos, Jesús ^a,b   Serrano Gotarredona, Teresa ^a   Serrano Gotarredona, Rafael ^a,c   Linares Barranco, Bernabé ^a  

^a INSTITUTO DE MICROELECTRÓNICA DE SEVILLA   (Spain)

^b National Centre for Education Information and Communication   (Spain)

^c NXP Semiconductors Austria GmbH   (Austria)

Author keywords

Address event representation (AER); Analog circuits; Artifical retina; Calibration; Contrast computation; Current mode circuits; Imagers; Low power circuits and systems; Mismatch; Neuromorphic circuits; Sensory systems; Trimming; Vision systems; Weak inversion circuits

Indexed keywords

ANALOG CIRCUITS; CALIBRATION; CMOS INTEGRATED CIRCUITS; COMPUTATIONAL METHODS; IMAGE SENSORS; PHOTOCURRENTS; PIXELS; VISION AIDS;

ADDRESS-EVENT REPRESENTATION; CONTRAST COMPUTATION; CURRENT-MODE CIRCUITS; MICROCHIP; NEUROMORPHIC CIRCUITS;

BIOCHIPS;

EID: 34547137658     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2007.900179     Document Type: Article

References (74)

1. M. Sivilotti, "Wiring considerations in analog VLSI systems with application to field-programmable networks," Ph.D. thesis, Comp. Sci. Div., California Institute of Technology, Pasadena, 1991.
2. M. Mahowald, "VLSI Analogs of neural visual processing: A synthesis of form and function," Ph.D. thesis, Comp. Sci. Div., California Institute of Technology, Pasadena, 1992.
3. J. Lazzaro, J.Wawrzynek, M. Mahowald, M. Sivilotti, and D. Gillespie, "Silicon auditory processors as computer peripherals," IEEE Trans. Neural Netw., vol. 4, no. 3, pp. 523-528, May 1993.
4. M. Mahowald, An Analog VLSI Stereoscopic Vision System. Reading, MA: Kluwer Academic, 1994.
5. J. P. Lazzaro and J.Wawrzynek, "A multi-sender asynchronous extension to the address-event protocol," in Proc. 16th Conf. Adv.Res. VLSI W. J. Dally, J. W. Poulton, and A. T. Ishii, Eds., 1995, pp. 158-169.
6. W. Maass and C. M. Bishop, Eds., Pulsed Neural Networks. Cambridge, MA: MIT Press, 1999.
7. S. Thorpe, D. Fize, and C. Marlot, "Speed of processing in the human visual system," Nature, vol. 381, no. 6582, pp. 520-522, Jun. 6, 1996.
8. P. F. Ruedi et al., "A 128 × 128, pixel 120-dB dynamic-range vision-sensor chip for image contrast and orientation extraction," IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2325-2333, Dec. 2003.
9. M. Barbaro, P. Y. Burgi, A. Mortara, P. Nussbaum, and F. Heitger, "A 100 × 100 pixel silicon retina for gradient extraction with steering filter capabilities and temporal output coding," IEEE J. Solid-State Circuits, vol. 37, no. 1, pp. 160-172, Jan. 2002.
10. A. Mortara and E. A. Vittoz, "A communication architecture tailored for analog VLSI artificial neural networks: Intrinsic performance and limitations," IEEE Trans. Neural Netw., vol. 5, no. 3, pp. 459-466, May 1994.
11. A. Mortara, E. A. Vittoz, and P. Venier, "A communication scheme for analog VLSI perceptive systems," IEEE J. Solid-State Circuits, vol. 30, no. 6, pp. 660-669, Jun. 1995.
12. Z. Kalayjian and A. G. Andreou, "Asynchronous communication of 2-D motion information using winner-takes-all arbitration," Int. J. Analog Integ. Circ. Sign. Proc., vol. 13, no. 1-2, pp. 103-109, Mar./ Apr. 1997.
13. K. A. Boahen, "Communicating neuronal ensembles between neuromorphic chips," in Neuromorphic Systems Engineering: Neural Networks in Silicon, T. S. Lande, Ed. Norwell, MA: Kluwer, 1998, ch. 11.
14. K. Boahen, "Point-to-point connectivity between neuromorphic chips using address events," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 47, no. 5, pp. 416-434, May 2000.
15. K. A. Boahen, "A burst-mode word-serial address-event link-I transmitter design," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 7, pp. 1269-1280, Jul. 2004.
16. K. A. Boahen, "A burst-mode word-serial address-event link-II: Receiver design," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 7, pp. 1281-1291, Jul. 2004.
17. K. A. Boahen, "A burst-mode word-serial address-event link-III: Analysis and test results," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 7, pp. 1292-1300, Jul. 2004.
18. E. Culurciello, R. Etienne-Cummings, and K. A. Boahen, "A biomorphic digital image sensor," IEEE J. Solid-State Circuits, vol. 38, no. 2, pp. 281-294, Feb. 2003.
19. C. Shoushun and A. Bermak, "A low power CMOS imager based on time-to-first-spike encoding and fair AER," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS'05), 2005, pp. 5306-5309.
20. X. G. Qi, X., and J. Harris, "A time-to-first-spike CMOS imager," in Proc. 2004 IEEE Int. Symp. Circuits Syst. (ISCAS2004 , Vancouver, Canada, 2004, pp. 824-827.
21. M. Azadmehr, J. Abrahamsen, and P. Häfliger, "A foveated AER imager chip," in Proc. IEEE Int. Symp. on Circuits Syst. (ISCAS2005), Kobe, Japan, 2005, pp. 2751-2754.
22. R. J. Vogelstein, U. Mallik, E. Culurciello, R. Etienne-Cummings, and G. Cauwenberghs, "Spatial acuity modulation of an address-event imager," in Proc. 2004 11th IEEE Int. Conf. Electronics, Circuits Syst. (ICECS 2004), Dec. 2004, pp. 207-210.
23. J. Kramer, "An integrated optical transient sensor," IEEE Trans. Circuits Syst., II. Analog Digit. Signal Process., vol. 49, no. 9, pp. 612-628, Sep. 2002.
24. P. Lichtsteiner, T. Delbrück, and J. Kramer, "Improved on/off temporally differentiating address-event imager," in Proc. 2004 IEEE Int. Symp. Circuits Syst. (ISCAS2004), Vancouver, Canada, 2004, pp. 211-214.
25. P. Lichtsteiner, C. Posch, and T. Delbruck, "A 128 × 128 120 dB 30 mW asynchronous vision sensor that responds to relative intensity change," in Dig. Tech. Papers IEEE ISSCC, San Francisco, CA, 2006, pp. 508-509.
26. M. Arias-Estrada, D. Poussart, and M. Tremblay, "Motion vision sensor architecture with asynchronous self-signaling pixels," in Proc. 7th Int. Workshop Computer Architecture for Machine Perception (CAMP97), 1997, pp. 75-83.
27. C. M. Higgins and S. A. Shams, "Abiologically inspired modular VLSI system for visual measurement of self-motion," IEEE Sensors J., vol. 2, no. 6, pp. 508-528, Dec. 2002.
28. E. Özalevli and C. M. Higgins, "Reconfigurable biologically inspired visual motion system using modular neuromorphic VLSI chips," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 1, pp. 79-92, Jan. 2005.
29. G. Indiveri, A. M. Whatley, and J. Kramer, "A reconfigurable neuromorphic VLSI multi-chip system applied to visual motion computation," in Proc. Int. Conf. Microelectronics for Neural, Fuzzy and Bio-Inspired Systems (Microneuro99), Granada, Spain, 1999, pp. 37-44.
30. K. Boahen, "Retinomorphic chips that see quadruple images," in Proc. Int. Conf. Microelectronics for Neural, Fuzzy and Bio-Inspired Systems (Microneuro99), Granada, Spain, 1999, pp. 12-20.
31. R. Z. Shi and T. K. Horiuchi, "A VLSI model of the bat dorsal nucleus of the lateral lemniscus for azimuthal echolocation," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS2005), Kobe, Japan, 2005.
32. A. van Schaik and S.-C. Liu, "AER EAR: A matched silicon cochlea pair with address event representation interface," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS2005), Kobe, Japan, 2005, pp. 4213-4216.
33. G. Cauwenberghs, N. Kumar, W. Himmelbauer, and A. G. Andreou, "An analog VLSI Chip with asynchronous interface for auditory feature extraction," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 45, no. 5, pp. 600-606, May 1998.
34. M. Oster and S.-C. Liu, "Spiking inputs to a spiking winner-take-all circuit," in Advances in Neural Information Processing Systems Y. Weiss, B. Schölkopf, and J. Platt, Eds. Cambridge, MA: MIT Press, 2006, vol. 18, pp. 1051-1058 Online. Available: Http:// www.books.nips.cc/papers/files/nips18/NIPS2005_0521.pdf, (NIPS'06)
35. J. Abrahamsen, P. Häfliger, and T. S. Lande, "A time domain winner-take-all network of integrate-and-fire neurons," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS04), Vancouver, Canada, May 2004, vol. V, pp. 361-364.
36. E. Chicca, G. Indiveri, and R. J. Douglas, "An event-based VLSI network of integrate-and-fire neurons," in Proc. IEEE Int. Symp. on Circuits Syst. (ISCAS2004), Vancouver, Canada, 2004, vol. V, pp. 357-360.
37. T. Teixeira, A. G. Andreou, and E. Culurciello, "Event-based imaging with active illumination in sensor networks," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS2005), Kobe, Japan, 2005, pp. 644-647.
38. R. Serrano-Gotarredona, T. Serrano-Gotarredona, A. Acosta-Jiménez, and B. Linares-Barranco, "A neuromorphic cortical layer microchip for spike-based event processing vision systems," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 12, pp. 2548-2566, Dec. 2006.
39. D. H. Goldberg, G. Cauwenberghs, and A. G. Andreou, "Probabilistic synaptic weighting in a reconfigurable network of VLSI integrate-and-fire neurons," Neural Netw., vol. 14, no. 6-7, pp. 781-793, 2001.
40. R. J. Vogelstein, U. Mallik, and G. Cauwenberghs, "Silicon spike-based synaptic array and address-event transceiver," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS'04), 2004, vol. 5, pp. 385-388.
41. R. J. Vogelstein, F. Tenore, R. Philipp, M. S. Adlerstein, D. H. Goldberg, and G. Cauwenberghs, "Spike timing-dependent plasticity in the address domain," in Advances in Neural Information Processing Systems, S. Becker, S. Thrun, and K. Obermayer, Eds. Cambridge, MA: MIT Press, 2003, vol. 15.
42. R. J. Vogelstein, U. Mallik, G. Cauwenberghs, E. Culurciello, and R. Etienne-Cummings, "Saliency-driven image acuity modulation on a reconfigurable silicon array of spiking neurons," in Advances in Neural Information Processing Systems, L. K. Saul, Y. Weiss, and L. Bottou, Eds. Cambridge, MA: MIT Press, 2005, vol. 17, pp. 1457-1464.
43. U. Mallik, R. J. Vogelstein, E. Culurciello, R. Etienne-Cummings, and G. Cauwenberghs, "Areal-time spike-domain sensory information processing system," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS'05), Kobe, Japan, 2005, pp. 1919-1922.
44. S.-C. Liu, J. Kramer, G. Indiveri, T. Delbrück, and R. Douglas, "Orientation-selective a VLSI spiking neurons," Neural Netw., vol. 14, pp. 629-643, 2001.
45. P. Vernier, A. Mortara, X. Arreguit, and E. A. Vittoz, "An integrated cortical layer for orientation enhancement," IEEE J. Solid-State Cicuits, vol. 32, pp. 177-186, Feb. 1997.
46. T. Serrano-Gotarredona, A. G. Andreou, and B. Linares-Barranco, "AER image filtering architecture for vision processing systems," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 46, no. 9, pp. 1064-1071, Sep. 1999.
47. T. Y. W. Choi, B. E. Shi, and K. Boahen, "An ON-OFF orientation selective address event representation image transceiver chip," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 2, pp. 342-353, Feb. 2004.
48. T. Y. W. Choi, P. A. Merolla, J. V. Arthur, K. A. Boahen, and B. E. Shi, "Neuromorphic implementation of orientation hypercolummns," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 6, pp. 1049-1060, Jun. 2005.
49. M. A. Mahowald and C. Mead, "Silicon retina," in Analog VLSI and Neural Systems, C. Mead, Ed. Reading: Addison Wesley, 1989, ch. 15, pp. 257-278.
50. A. G. Andreou and K. A. Boahen, "A 590,000 transistor 48,000 pixel, contrast sensitive, edge enhancing, CMOS imager-silicon retina," in Proc. 16th Conf. on Advanced Research in VLSI (ARVLSI'95), 1995, p. 225.
51. K. A. Zaghloul and K. Boahen, "Optic nerve signals in a neuromorphic chip: Parts 1," IEEE Trans. Biomed Eng., vol. 51, pp. 657-666, 2004.
52. K. A. Zaghloul and K. Boahen, "Optic nerve signals in a neuromorphic chip: Part 2," IEEE Trans. Biomed Eng., vol. 51, pp. 667-675, 2004.
53. R. H. Nixon, S. E. Kemeny, B. Pain, C. O. Staller, and E. R. Fossum, "256 × 256 CMOS active pixel sensor camera-on-a-chip," IEEE J. Solid-State Circuits, vol. 31, pp. 2046-2050, Dec. 1996.
54. G. Jun, C. Zhungjian, L. Wengao, and J. Lijiu, "Correlated-double-sampling design for CMOS image readout integrated circuits," in Proc. 7th Int. Conf. Solid-State Integrated Circuits Technol., Oct. 2004, vol. 2, pp. 1437-1440.
55. S. Kavadias, B. Dierickx, D. Scheffer, A. Alaerts, D. Uwaerts, and J. Bogaerts, "A logarithmic response CMOS image sensor with on-chip calibration," IEEE J. Solid-State Circuits, vol. 35, no. 8, pp. 1146-1152, Aug. 2000.
56. M. Loose, K. Meier, and J. Schemmel, "A self-calibrating single-chip CMOS camera with logarithmic response," IEEE J. Solid-State Circuits vol. 36, no. 4, pp. 586-596, Apr. 2001.
57. B. Linares-Barranco, T. Serrano-Gotarredona, and R. Serrano-Gotarredona, "Compact low-power calibration mini-DACs for neural massive arrays with programmable weights," IEEE Trans. Neural Netw., vol. 14, no. 5, pp. 1207-1216, Sep. 2003.
58. K. A. Boahen and A. G. Andreou, "A contrast sensitive silicon retina with reciprocal synapses," in Advances in Neural Information Processing Systems. San Mateo: Morgan Kaufmann Publishers, 1992, vol. 4, pp. 764-772, (NIPS 1991).
59. J. E. Dowling, The Retina: An Approachable Part of the Brain. Cambridge, MA: Harvard University Press, 1987.
60. S. Grossberg, E. Mingolla, and J. Williamson, "Synthetic aperture radar processing by a multiple scale neural system for boundary and surface representation," Neural Netw., vol. 8, no. 7/8, pp. 1005-1028, 1995.
61. B. Linares-Barranco, T. Serrano-Gotarredona, R. Serrano-Gotarredona, and C. Serrano-Gotarredona, "Current-mode techniques for sub-pico-ampere circuit design," Int. J. Analog Integr. Circuits Signal Process., vol. 38, pp. 103-119, 2004.
62. B. Linares-Barranco and T. Serrano-Gotarredona, "On the design and characterization of femtoampere current-mode circuits," IEEE J. Solid-State Circuits, vol. 38, no. 8, pp. 1353-1363, Aug. 2003.
63. C. Mead, Analog VLSI and Neural Systems. Boston, MA: Addison Wesley, 1989.
64. A. G. Andreou, "On physical models of neural computation and their analog VLSI implementation," in Workshop on Physics and Computation, IEEE Computer Society, Dallas, Nov. 1994, pp. 255-264.
65. E. Vittoz and X. Arreguit, "Linear networks based on transistors," Electron. Lett., vol. 29, pp. 297-299, Feb. 1993.
66. A. G. Andreou and K. Boahen, "Translinear circuits in subthreshold CMOS," in Analog Integrated Circuits and Signal Processing.: Kluwer, Apr. 1996, pp. 141-166, no. 9.
67. S.-C. Liu, J. Kramer, G. Indiveri, T. Delbrück, and R. Douglas, Analog VLSI: Circuits and Principles. Cambridge, MA: The MIT Press, 2002.
68. T. Serrano-Gotarredona and B. Linares-Barranco, "CMOS mismatch model valid from weak to strong inversion," in Proc. 2003 Eur. Solid-State Circuits Conf. (ESSCIRC'03), Sep. 2003, pp. 627-630.
69. K. Bult and J. G. M. Geelen, "An inhenrently linear and compact MOST-only current division technique," IEEE J. Solid-State Circuits vol. 27, pp. 1730-1735, Dec. 1992.
70. C. C. Enz and E. A. Vittoz, "CMOS low-power analog circuit design," in Proc. Int. Symp. Circuits Syst. (ISCAS'96), 1996, pp. 79-132, Tutorials, ch. 1.2.
71. A. Moini, Vision Chips. Norwell, MA: Kluwer, 1999.
72. F. Gomez-Rodriguez, R. Paz-Vicente, A. Linares-Barranco, M. Rivas, L. Miro, S. Vicente, G. Jiménez, and A. Civit, "AER tools for communications and debugging," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS 2006), Kos, Greece, May 2006, pp. 3253-3256.
73. A. Linares-Barranco, G. Jimenez-Moreno, B. Linares-Barranco, and A. Civit-Ballcels, "On algorithmic rate-coded AER generation," IEEE Trans. Neural Netw., vol. 17, no. 3, pp. 771-788, May 2006.
74. R. Serrano-Gotarredona, M. Oster, P. Lichtsteiner, A. Linares-Barranco, R. Paz-Vicente, F. Gömez-Rodríguez, H. Kolle Riis, T. Delbrück, S. C. Liu, S. Zahnd, A. M. Whatley, R. Douglas, P. Häfliger, G. Jimenez-Moreno, A. Civit, T. Serrano-Gotarredona, A. Acosta-Jiménez, and B. Linares-Barranco, "AER building blocks for multi-layers multi-chips neuromorphic vision systems," in Advances in Neural Information Processing Systems, Y. Weiss, B. Schölkopf, and J. Platt, Eds. Cambridge, MA: MIT Press, 2006, vol. 18, pp. 1217-1224 Online. Available: Http://www.books.nips.cc/papers/files/nips18/NIPS2005_0268.pdf, (NIPS'06)