A 100 × 100 pixel silicon retina for gradient extraction with steering filter capabilities and temporal output coding

IEEE Journal of Solid-State Circuits

Volumn 37, Issue 2, 2002, Pages 160-172

  Barbaro, Massimo ^a   Burgi, Pierre Yves ^b   Mortara, Alessandro ^b   Nussbaum, Pascal ^b   Heitger, Friedrich ^b  

^a UNIVERSITY OF CAGLIARI   (Italy)

^b CSEM   (Switzerland)

Author keywords

Analog VLSI design; Artificial retina; Early vision; Image processing; Spatial gradient extraction; Steerable filters; Temporal coding

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; IMAGE PROCESSING; IMAGE SENSORS;

SPATIAL GRADIENT EXTRACTION; TEMPORAL CODING;

VLSI CIRCUITS;

EID: 0036474823     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.982422     Document Type: Article

References (24)

1. Analog hardware for detecting discontinuities in early vision
2. Analog VLSI systems for image acquisition and fast early vision processing
3. Analog VLSI neuromorphic image acquisition and pre-processing systems
4. A new structure of the 2-D silicon retina
5. Analog VLSI circuits as physical structures for perception in early visual tasks
6. A CMOS vision chip with SIMD processing element array for 1 ms image processing
7. A foveated silicon retina for two-dimensional tracking
8. Focal plane implementation of 2D steerable and scalable Gabor-type filters
9. Computation of orientational filters for real-time computer vision problems - III: Steerable system and VLSI architecture
10. Occlusions and their relationship with the distribution of contrasts in natural images
11. What is the goal of sensory coding?
12. Asynchrony in image analysis: Using the luminance-to-response-latency relationship to improve segmentation
13. The design and use of steerable filters
14. A 12-transistor PFM demodulator for analog neural networks communication
15. Analog VLSI signal processing: Why, where and how?
16. Pseudo-resistive networks and their applications to analog collective computation
17. Micropower techiques
18. High-resolution current comparators: Design and application to current-mode function generation
19. A communication scheme for analog VLSI perceptive systems
20. A fast 100 × 100 pixel silicon retina for edge extraction with application in OCR
21. A programmable focal-plane MIMD image processor chip
22. A VLSI sorting image sensor: Global massively parallel intensity-to-time processing for low-latency adaptive vision