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Nano Letters
Volumn 7, Issue 3, 2007, Pages 773-777
Layer-by-layer assembly of nanowires for three-dimensional, multifunctional electronics
Author keywords

[No Author keywords available]
Indexed keywords

MULTIFUNCTIONAL CIRCUITRY; PLASTIC SUBSTRATES; SEQUENTIAL STACKING; SIGNAL INVERSION;
EID: 34047143923     PISSN: 15306984     EISSN: None     Source Type: Journal    
DOI: 10.1021/nl063056l     Document Type: Article
Times cited : (577)
References (43)
  • 5
  • 6
    • 21144442707 scopus 로고    scopus 로고
    • (c) Yang, P. MRS Bull. 2005, 30, 85.
    • (2005) MRS Bull , vol.30 , pp. 85
    • Yang, P.1
  • 30
    • 34047148579 scopus 로고    scopus 로고
    • NWs were printed by sliding a growth substrate, which consists of a lawn of Ge/Si core/shell NWs (diameter, ∼15 nm; length, ∼30 μm, against a second device substrate (Si/SiO2 or Kapton, The Ge/Si NWs are randomly oriented on the growth substrate, not epitaxial, and are well-aligned by sheer forces during the sliding process. The sliding process results in the direct and dry transfer of NWs from the growth substrate to the desired device substrate chip. Prior to transfer, the device substrate was patterned with a photoresist layer ∼500 nm thickness, Shipley 1805, The patterned spacer serves as dual purpose: to prevent transfer of particles and low-quality NW material close to the surface of the growth chip, and to enable selective assembly of the NWs at defined locations. After transfer, the patterned photoresist is removed in acetone, leaving only patterned NWs, which are well-aligned along the sliding direction
    • 2 or Kapton). The Ge/Si NWs are randomly oriented on the growth substrate, not epitaxial, and are well-aligned by sheer forces during the sliding process. The sliding process results in the direct and dry transfer of NWs from the growth substrate to the desired device substrate chip. Prior to transfer, the device substrate was patterned with a photoresist layer (∼500 nm thickness, Shipley 1805). The patterned spacer serves as dual purpose: to prevent transfer of particles and low-quality NW material close to the surface of the growth chip, and to enable selective assembly of the NWs at defined locations. After transfer, the patterned photoresist is removed in acetone, leaving only patterned NWs, which are well-aligned along the sliding direction.
  • 31
    • 34047146183 scopus 로고    scopus 로고
    • The FET structures were defined by two photolithography (PL) steps. In the first PL step, the source/drain (S/D) electrodes were patterned and metallized with Ni (60 nm, A HfO2 high-κ gate dielectric film (thickness, ∼12 nm) was deposited by 100 cycles of ALD at 115°C with each cycle consisting of 1 s water vapor pulse, 5 s N2 purge, 3 s tetrakis(dimethylamino)hafnium [Hf(N(CH3)2)4] pulse, and 5 s N2 purge. In the second PL step, the top gates were patterned and metallised with Al (60 nm, For multilayer structures, a SiO 2 layer ∼300 nm, which serves as a separation layer between active device layers, was deposited by plasma-enhanced CVD or e-beam evaporation. Each additional active NW layer was offset in x and y directions to facilitate imaging and electrical measurements
    • 2 layer (∼300 nm), which serves as a separation layer between active device layers, was deposited by plasma-enhanced CVD or e-beam evaporation. Each additional active NW layer was offset in x and y directions to facilitate imaging and electrical measurements.
  • 33
    • 34047177648 scopus 로고    scopus 로고
    • Measurements were conducted with a probe station (model 12561B, Cascade Microtech) and a semiconductor parameter analyzer (model 4156C, Agilent). For AC characterization of the inverters, a function generator (model 8648B, Agilent) was used to provide high-frequency voltage pulses for the input, while the output voltage was monitored by an oscilloscope (model TDS3012, Tektronix) using a high-impedance FET probe (model 12C, Picoprobe).
    • Measurements were conducted with a probe station (model 12561B, Cascade Microtech) and a semiconductor parameter analyzer (model 4156C, Agilent). For AC characterization of the inverters, a function generator (model 8648B, Agilent) was used to provide high-frequency voltage pulses for the input, while the output voltage was monitored by an oscilloscope (model TDS3012, Tektronix) using a high-impedance FET probe (model 12C, Picoprobe).
  • 39
    • 0003797611 scopus 로고    scopus 로고
    • Brown, W. D, Brewer J. E, Eds, IEEE Press: New York
    • NonVolatile Semiconductor Memory Technology; Brown, W. D., Brewer J. E., Eds.; IEEE Press: New York, 1998.
    • (1998) NonVolatile Semiconductor Memory Technology
  • 40
    • 34047154736 scopus 로고    scopus 로고
    • 2 layer is used as the intergate oxide.
    • 2 layer is used as the intergate oxide.
  • 43
    • 19744381480 scopus 로고    scopus 로고
    • Fazio, A. MRS Bull. 2004, 29, 814.
    • (2004) MRS Bull , vol.29 , pp. 814
    • Fazio, A.1

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.