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Volumn 4, Issue 3, 2004, Pages 416-421

Evaluation of SiO2 antifuse in a 3D-OTP memory

Author keywords

3d memory; Antifuse; Archival media; Nonvolatile memory; Oxide breakdown

Indexed keywords

CMOS INTEGRATED CIRCUITS; MIM DEVICES; NONVOLATILE STORAGE; POLYSILICON; PROM; SEMICONDUCTOR DEVICES;

EID: 11144243668     PISSN: 15304388     EISSN: None     Source Type: Journal    
DOI: 10.1109/TDMR.2004.837118     Document Type: Article
Times cited : (28)

References (26)
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    • Current status of the phase change memory and its future
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    • Data retention, endurance and acceleration factors of NROM devices
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    • D. K. Y. Liu, K. L. Chen, H. Tigelaar, J. Paterson, and S. O. Chen, "Scaled dielectric antifuse structure for field-programmable gate array applications," IEEE Electron. Device Lett., vol. 12, pp. 151-153, Apr. 1991.
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    • Liu, D.K.Y.1    Chen, K.L.2    Tigelaar, H.3    Paterson, J.4    Chen, S.O.5
  • 19
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    • Three-Transistor one-time programmable (OTP) ROM cell array using standard CMOS gate oxide antifuse
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    • J. Kim and K. Lee, "Three-Transistor one-time programmable (OTP) ROM cell array using standard CMOS gate oxide antifuse," IEEE Electron. Device Lett., vol. 24, pp. 589-591, Sept. 2003.
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    • Acceleration factors and mechanistic study of progressive breakdown in small area ultra-thin gate oxides
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.