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Volumn 2002-January, Issue , 2002, Pages 419-424

Time-domain simulation of variational interconnect models

Author keywords

Admittance; Circuit simulation; Integrated circuit interconnections; Linear systems; Nonlinear circuits; Reduced order systems; Stability; Time domain analysis; Vectors; Voltage

Indexed keywords

CIRCUIT SIMULATION; CONVERGENCE OF NUMERICAL METHODS; ELECTRIC ADMITTANCE; ELECTRIC NETWORK ANALYSIS; ELECTRIC POTENTIAL; INTEGRATED CIRCUIT INTERCONNECTS; LINEAR SYSTEMS; NONLINEAR ANALYSIS; VECTORS;

EID: 84948468889     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2002.996782     Document Type: Conference Paper
Times cited : (16)

References (10)
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  • 2
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    • Odabasioglu, A.1    Celik, M.2    Pileggi, L.T.3
  • 3
    • 84893805172 scopus 로고    scopus 로고
    • Model-order reduction of RC(L) interconnect including variational analysis
    • Liu, Y., et al. "Model-order reduction of RC(L) interconnect including variational analysis", Proc. IEEE/ACM DAC, 1999.
    • (1999) Proc. IEEE/ACM DAC
    • Liu, Y.1
  • 5
    • 84893793807 scopus 로고    scopus 로고
    • TETA: Transistor-level waveform evaluation engine for timing analysis
    • Acar. E., F. Dartu, and L. T. Pileggi, "TETA: Transistor-level waveform evaluation engine for timing analysis", to appear in IEEE Trans. on CAD.
    • IEEE Trans. on CAD
    • Acar, E.1    Dartu, F.2    Pileggi, L.T.3
  • 6
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    • SPICE3 Manual, http://www.eecs.berkeley.edu/~spice.
    • SPICE3 Manual
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  • 8
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    • Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSIs
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    • Sakurai, T. "Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSIs", IEEE Trans. ED, vol 40. Jan 1993.
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  • 9
    • 84893763621 scopus 로고    scopus 로고
    • Impact of interconnect variations on the clock skew of a gigahertz microprocessor
    • Liu, Y. et al. "Impact of interconnect variations on the clock skew of a gigahertz microprocessor", Proc. IEEE/ACM DAC, 2000.
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  • 10
    • 84949955220 scopus 로고    scopus 로고
    • Assessment of true worst case circuit performance under interconnect parameter variations
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.