Impact of within-die parameter fluctuations on future maximum clock frequency distributions

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2001, Pages 229-232

  Bowman, K A ^a   Meindl, J D ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; GATES (TRANSISTOR); LOGIC GATES; MICROPROCESSOR CHIPS; MOSFET DEVICES; NORMAL DISTRIBUTION; STATISTICAL METHODS;

GENERIC CRITICAL PATH MODEL; MAXIMUM CLOCK FREQUENCY DISTRIBUTIONS; WITHIN DIE FLUCTUATIONS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0034823025     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

1. Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution
2. Statistical circuit modeling and optimization
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5. A physical alpha-power law MOSFET model
6. Opportunities for scaling FET's for gigascale integration (GSI)
7. High-performance microprocessor design
8. Low power microelectronics: Retrospect and prospect
9. Delay analysis of series-connected MOSFET circuits
10. Technology and design challenges for low power and high performance
11. Intra-field gate CD variability and its impact on circuit performance