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Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2002-January, Issue , 2002, Pages 129-132

Impact analysis of process variability on clock skew

(6) Malavasi, Enrico a Zanella, Stefano a Cao, Min a Uschersohn, Julian a Misheloff, Mike a Guardiani, Carlo a

Author keywords

Analytical models; Circuit analysis computing; Circuit simulation; Clocks; Computational modeling; Computer networks; Performance analysis; Process design; Statistical analysis; Tree data structures

Indexed keywords

ANALYTICAL MODELS; CIRCUIT SIMULATION; CLOCKS; COMPUTER NETWORKS; DESIGN; ELECTRIC CLOCKS; EXTRACTION; FORESTRY; PROCESS DESIGN; STATISTICAL METHODS; TOPOLOGY; TREES (MATHEMATICS);

CIRCUIT-LEVEL SIMULATION; COMPUTATIONAL MODEL; PARASITIC EXTRACTION; PERFORMANCE ANALYSIS; PROCESS VARIABILITY; TOPOLOGICAL ANALYSIS; TREE DATA STRUCTURES; VARIATIONAL ANALYSIS;

ELECTRIC NETWORK ANALYSIS;

EID: 84948459207 PISSN: 19483287 EISSN: 19483295 Source Type: Journal
DOI: 10.1109/ISQED.2002.996712 Document Type: Article

Times cited : (16)

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- Impact Analysis of Process Variability on Digital Circuits with Performance Limited Yield
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