Scalable and multibias high frequency modeling of multi-fin FETs

Solid-State Electronics

Volumn 50, Issue 11-12, 2006, Pages 1780-1786

  Crupi, G ^a   Schreurs, D ^b   Parvais, B ^c   Caddemi, A ^a   Mercha, A ^c   Decoutere, S ^c  

^a UNIVERSITY OF MESSINA   (Italy)

^b UNIVERSITY OF LEUVEN   (Belgium)

^c IMEC   (Belgium)

Author keywords

Equivalent circuit model; FinFET; Multi bias; Multi fins; Scalability; Scattering parameters

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK ANALYSIS; EQUIVALENT CIRCUITS; SCATTERING PARAMETERS;

EQUIVALENT CIRCUIT MODELS; FINFET; MULTIFINS; SCALABILITY;

FIELD EFFECT TRANSISTORS;

EID: 33751224205     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2006.09.006     Document Type: Article

References (31)

1. Yang F.L., Chen H.Y., Chen F.C., Huang C.C., Chang C.Y., Chiu H.K., et al. 25 nm CMOS Omega FETs. IEDM Tech Dig (2002) 255-258
2. Doyle B.S., Datta S., Doczy M., Hareland S., Jin B., Kavalieros J., et al. High performance fully-depleted tri-gate CMOS transistors. IEEE Electron Dev Lett 24 4 (2003) 263-265
3. Park J., and Colinge J.P. Multiple-gate SOI MOSFETs: Device design guidelines. IEEE Trans Electron Dev 49 12 (2002) 2222-2229
4. Dixit A., Kottantharayil A., Collaert N., Goodwin M., Jurczak M., and De Meyer K. Analysis of the parasitic source/drain resistance in multiple gate field effect transistors. IEEE Trans Electron Dev 52 6 (2005) 1131-1140
5. Hisamoto D., Lee W.C., Kedzierski J., Anderson E., Takeuchi H., Asano K., et al. A folded-channel MOSFET for deep-sub-tenth micron era. IEDM Tech Dig (1998) 1032-1034
6. Huang X., Lee W.C., Kuo C., Hisamoto D., Chang L., Kedzierski J., et al. Sub 50-nm FinFet: PMOS. IEDM Tech Dig (1999) 67-70
7. Hisamoto D., Lee W.C., Kedzierski J., Takeuchi H., Asano K., Kuo C., et al. FinFet - A self-aligned double-gate MOSFET scalable to 20 nm. IEEE Trans Electron Dev 47 12 (2000) 2320-2325
8. Lederer D., Kilchytska V., Rudenko T., Collaert N., Flandre D., Dixit A., et al. FinFET analogue characterization from DC to 110 GHz. Solid-State Electron 49 9 (2005) 1488-1496
9. Woo D.S., Choi B.Y., Choi W.Y., Lee M.W., Lee J.D., and Park B.G. 30 nm self-aligned FinFET with large source/drain fan-out structure. Electron. Lett 39 15 (2003) 1154-1155
10. Woo D.S., Lee J.H., Choi W.Y., Choi B.Y., Choi Y.J., Lee J.D., et al. Electrical characteristics of FinFET with vertically nonuniform source/drain doping profile. IEEE Trans Nanotech 1 4 (2002) 233-237
11. Kilchytska V., Collaert N., Rooyackers R., Lederer D., Raskin J.P., and Flandre D. Perspective of FinFETs for analog applications. ESSDERC (2004) 65-68
12. Lederer D., Parvais B., Mercha A., Collaert N., Jurczak M., Raskin J.P., et al. Dependence of FinFET RF performance on fin width. IEEE Silicon Monolithic Integr Circ RF Syst (2006) 8-11
13. Parvais B., Gustin C., De Heyn V., Loo J., Dehan M., Subramanian V., et al. Suitability of FinFET technology for low-power mixed-signal applications. ICICDT (2006) 7-79
14. Subramanian V., Mercha A., Parvais B., Loo J., Gustin C., Dehan M., et al. Optimization of FinFET geometries for analog performance. ULIS (2006) 21-24
15. Colinge J.P. Multiple-gate SOI MOSFETs. Solid-State Electron 48 6 (2004) 897-905
16. Vandamme E.P., Schreurs D., van Dinther C., Badenes G., and Deferm L. Development of a RF large signal MOSFET model, based on an equivalent circuit, and comparison with BSIM3v3 compact model. Solid-State Electron 46 3 (2002) 353-360
17. Orzati A., Schreurs D., Pergola L., Benedickter H., Robin F., Homan O., et al. A 110-GHz large-signal lookup-table model for InP HEMTs including impact ionization effects. IEEE Trans Microwave Theory Technol 51 2 (2003) 468-474
18. Joshi R.V., Pascual-Gutierrez J.A., and Chuang C.T. 3-D thermal modeling of finFET. IEEE Solid-State Device Res Conf (2005) 77-80
19. Caddemi A., Crupi G., and Donato N. Impact of the self-generated heat on the scalability of HEMTs. Microelectron Eng 82 2 (2005) 143-147
20. Caddemi A., Crupi G., and Donato N. Temperature effects on DC and small signal RF performance of AlGaAs/GaAs HEMTs. Microelectron Reliab 46 1 (2006) 169-173
21. Alvaro M., Caddemi A., Crupi G., and Donato N. Temperature and bias investigation of self heating effect and threshold voltage shift in pHEMT's. Microelectron J 36 8 (2005) 732-736
22. Raskin J.P., Dambrine G., and Gillon R. Direct extraction of the series equivalent circuit parameters for the small-signal model of SOI MOSFET's. IEEE Microwave Guid Wave Lett 7 12 (1997) 408-410
23. Dambrine G., Cappy A., Heliodore F., and Playez E. A new method for determining the FET small-signal equivalent circuit. IEEE Trans Microwave Theory Technol 36 7 (1988) 1151-1159
24. Pascht A., Grözing M., Wiegner D., and Berroth M. Small-signal and temperature noise model for MOSFETs. IEEE Trans Microwave Theory Technol 50 8 (2002) 1927-1934
25. Bracale A., Ferlet-Cavrois V., Fel N., Pasquet D., Gautier J.L., Pelloie J.L., et al. A new approach for SOI devices small signal parameters extraction. Analog Integr Circ Signal Process (2000) 157-169
26. Giannini F, Graglia F, Leuzzi G, Serino A. Accurate microwave characterisation of power LD-MOSFETs. Gallium Arsenide applications symposium; 2000. 4 p.
27. Chan M, Taur Y, Lin CH, He J, Niknejad AM, Hu C. A framework for generic physics based double-gate MOSFET modeling. In: 6th International Conference on Modeling and Simulation of Microsystems; 2003:270-3.
28. Baccarani G., and Reggiani S. A compact double-gate MOSFET model comprising quantum-mechanical and nonstatic effects. IEEE Trans Electron Dev 46 8 (1999) 1656-1666
29. Fossum J.G., Ge L., Chiang M.H., Trivedi V.P., Chowdhury M.M., Mathew L., et al. A process/physics-based compact model for nonclassical CMOS device and circuit design. Solid-State Electron 48 6 (2004) 919-926
30. Sakalas P., Zirath H., Litwin A., Schröter M., and Matulionis A. Impact of pad and gate parasitics on small-signal and noise modeling of 0.35 μm gate length MOS transistors. IEEE Trans Electron Dev 49 5 (2002) 871-880
31. Rohdin H., Moll N., Su C.Y., and Lee G.S. Interfacial gate resistance in Schottky-Barrier-gate field-effect transistors. IEEE Trans Electron Dev 45 12 (1998) 2407-2416