-
1
-
-
0036149148
-
International technology roadmap for semiconductors (ITRS)
-
Allan, A.: et al. ' International technology roadmap for semiconductors (ITRS) ', Computers, 2002, p. 42-53
-
(2002)
Computers
, pp. 42-53
-
-
Allan, A.1
-
2
-
-
0003805836
-
-
Computer Science Press, Woodland Hills, CA, USA
-
Breuer, M.A., and Friedmzan, A.D.: ' Diagnosis and reliable design of digital systems ', (Computer Science Press, Woodland Hills, CA, USA 1976)
-
(1976)
Diagnosis and Reliable Design of Digital Systems
-
-
Breuer, M.A.1
Friedmzan, A.D.2
-
3
-
-
0003784677
-
-
ComTex Publishing, Gouda, The Netherlands, 2nd edn.
-
van de Goor, A.J.: ' Testing semiconductor memories, theory and practice ', 2nd (ComTex Publishing, Gouda, The Netherlands 1998)
-
(1998)
Testing Semiconductor Memories, Theory and Practice
-
-
Van De Goor, A.J.1
-
4
-
-
0020278451
-
Simple and efficient algorithms for functional RAM testing
-
Marinescu, M.: ' Simple and efficient algorithms for functional RAM testing ', Proc. Int. Test Conf., 1982, p. 236-239
-
(1982)
Proc. Int. Test Conf.
, pp. 236-239
-
-
Marinescu, M.1
-
5
-
-
0012573072
-
An optimal algorithm for testing stuck-at faults random access memories
-
Nair, R.: ' An optimal algorithm for testing stuck-at faults random access memories ', IEEE Trans. Comput., 1979, C-28, (3), p. 258-261
-
(1979)
IEEE Trans. Comput.
, vol.C-28
, Issue.3
, pp. 258-261
-
-
Nair, R.1
-
6
-
-
0019030541
-
A march test for functional faults in semiconductors random-access memories
-
Suk, D.S., and Reddy, S.M.: ' A march test for functional faults in semiconductors random-access memories ', IEEE Trans. Comput., 1980, C-29, (6), p. 419-429
-
(1980)
IEEE Trans. Comput.
, vol.C-29
, Issue.6
, pp. 419-429
-
-
Suk, D.S.1
Reddy, S.M.2
-
7
-
-
0022012145
-
An improved method for detecting functional faults in random access memories
-
Papachristou, C.A., and Saghal, N.B.: ' An improved method for detecting functional faults in random access memories ', IEEE Trans. Comput., 1985, C-34, (2), p. 110-116
-
(1985)
IEEE Trans. Comput.
, vol.C-34
, Issue.2
, pp. 110-116
-
-
Papachristou, C.A.1
Saghal, N.B.2
-
8
-
-
0019689426
-
Test procedure for a class of patterns sensitive faults in semiconductors random-access memories
-
Suk, D.S., and Reddy, S.M.: ' Test procedure for a class of patterns sensitive faults in semiconductors random-access memories ', IEEE Trans. Comput., 1981, C-30, (12), p. 982-985
-
(1981)
IEEE Trans. Comput.
, vol.C-30
, Issue.12
, pp. 982-985
-
-
Suk, D.S.1
Reddy, S.M.2
-
9
-
-
27644592104
-
Modeling of lithography related yield losses for CAD of VLSI circuits
-
Maly, W.: ' Modeling of lithography related yield losses for CAD of VLSI circuits ', IEEE Trans. CAD, 1985, 4, (3), p. 166-177
-
(1985)
IEEE Trans. CAD
, vol.4
, Issue.3
, pp. 166-177
-
-
Maly, W.1
-
10
-
-
0022201294
-
Inductive fault analysis of CMOS integrated circuits
-
Shen, J.P.: ' Inductive fault analysis of CMOS integrated circuits ', IEEE Des. Test Comput., 1985, 2, (6), p. 13-26
-
(1985)
IEEE Des. Test Comput.
, vol.2
, Issue.6
, pp. 13-26
-
-
Shen, J.P.1
-
11
-
-
0025442736
-
A realistic fault models and test algorithms for static random access memories
-
Dekker, R., Beenker, F., and Thijssen, H.: ' A realistic fault models and test algorithms for static random access memories ', IEEE Trans. Comput., 1990, C9, (6), p. 567-572
-
(1990)
IEEE Trans. Comput.
, vol.9
, Issue.6
, pp. 567-572
-
-
Dekker, R.1
Beenker, F.2
Thijssen, H.3
-
12
-
-
0030649559
-
False write through and un-restored write electrical level fault models for SRAMs
-
Adams, R.D., and Cooley, E.S.: ' False write through and un-restored write electrical level fault models for SRAMs ', Proc. IEEE Int. Workshop on Memory Technology, Design, and Testing, 1997, p. 27-32
-
(1997)
Proc. IEEE Int. Workshop on Memory Technology, Design, and Testing
, pp. 27-32
-
-
Adams, R.D.1
Cooley, E.S.2
-
13
-
-
0020811741
-
Functional testing of semiconductor random access memories
-
Abadir, M.S., and Reghbati, J.K.: ' Functional testing of semiconductor random access memories ', ACM Comput. Surv., 1983, 15, (3), p. 175-198
-
(1983)
ACM Comput. Surv.
, vol.15
, Issue.3
, pp. 175-198
-
-
Abadir, M.S.1
Reghbati, J.K.2
-
14
-
-
0003234909
-
Analysis of a deceptive read destructive memory fault model and recommended testing
-
Adams, R.D., and Cooley, E.S.: ' Analysis of a deceptive read destructive memory fault model and recommended testing ', Proc. IEEE North Atlantic Test Workshop, 1996
-
(1996)
Proc. IEEE North Atlantic Test Workshop
-
-
Adams, R.D.1
Cooley, E.S.2
-
15
-
-
0142144048
-
-
(Kluwer Academic Publisher), ISBN: 1-4020-7255-
-
Adams, R.D.: ' High performance memory testing ', (Kluwer Academic Publisher 2003), p. 4 ISBN: 1-4020-7255-
-
(2003)
High Performance Memory Testing
, pp. 4
-
-
Adams, R.D.1
-
16
-
-
0016952842
-
Moving inversions test pattern is thorough, yet speedy
-
De Jonge, J.H., and Smeulders, A.J.: ' Moving inversions test pattern is thorough, yet speedy ', Comput. Des., 1976, p. 169-173
-
(1976)
Comput. Des.
, pp. 169-173
-
-
De Jonge, J.H.1
Smeulders, A.J.2
-
17
-
-
0034505514
-
Experimental analysis of spot defects in SRAMs: Realistic fault models and tests
-
Hamdioui, S., and van de Goor, A.J.: ' Experimental analysis of spot defects in SRAMs: realistic fault models and tests ', Proc. Ninth Asian Test Symp., 2000, p. 131-138
-
(2000)
Proc. Ninth Asian Test Symp.
, pp. 131-138
-
-
Hamdioui, S.1
Van De Goor, A.J.2
-
19
-
-
0033331049
-
On comparing functional fault coverage and defect coverage for memory testing
-
Kim, V.K., and Chen, T.: ' On comparing functional fault coverage and defect coverage for memory testing ', IEEE Trans. CAD, 1999, 18, (11), p. 1676-1683
-
(1999)
IEEE Trans. CAD
, vol.18
, Issue.11
, pp. 1676-1683
-
-
Kim, V.K.1
Chen, T.2
-
20
-
-
0033352919
-
Industrial evaluation of stress combinations for march tests applied to SRAMs
-
Schanstra, I., and van de Goor, A.J.: ' Industrial evaluation of stress combinations for march tests applied to SRAMs ', Proc. IEEE Int. Test Conf., 1999, p. 983-992
-
(1999)
Proc. IEEE Int. Test Conf.
, pp. 983-992
-
-
Schanstra, I.1
Van De Goor, A.J.2
-
23
-
-
0037340134
-
Static and dynamic behavior of memory cell array spot defects in embedded DRAMs
-
Al-ars, Z., and van de Goor, A.J.: ' Static and dynamic behavior of memory cell array spot defects in embedded DRAMs ', IEEE Trans. Comput., 2003, 52, (3), p. 293-309
-
(2003)
IEEE Trans. Comput.
, vol.52
, Issue.3
, pp. 293-309
-
-
Al-Ars, Z.1
Van De Goor, A.J.2
-
24
-
-
0033750078
-
Functional fault models: A formal notation and taxonomy
-
van de Goor, A.J., and Al-Ars, Z.: ' Functional fault models: a formal notation and taxonomy ', Proc. IEEE VLSI Test Symp., 2000, p. 281-289
-
(2000)
Proc. IEEE VLSI Test Symp.
, pp. 281-289
-
-
Van De Goor, A.J.1
Al-Ars, Z.2
-
25
-
-
84881279108
-
Testing static and dynamic faults in random access memories
-
Hamdioui, S., Al-ars, Z., and van de Goor, A.J.: ' Testing static and dynamic faults in random access memories ', Proc. IEEE VLSI Test Symp., 2002, p. 395-400
-
(2002)
Proc. IEEE VLSI Test Symp.
, pp. 395-400
-
-
Hamdioui, S.1
Al-Ars, Z.2
Van De Goor, A.J.3
-
26
-
-
33645509946
-
A fault primitive based analysis of linked faults in RAMs
-
Al-ars, Z., Hamdioui, S., and van de Goor, A.J.: ' A fault primitive based analysis of linked faults in RAMs ', Proc. IEEE Int. Workshop on Memory Technology, Design, and Testing, 2003, p. 33-28
-
(2003)
Proc. IEEE Int. Workshop on Memory Technology, Design, and Testing
, pp. 33-28
-
-
Al-Ars, Z.1
Hamdioui, S.2
Van De Goor, A.J.3
-
27
-
-
2542437881
-
Linked faults in random-access-memories: Concept, fault models, test algorithms and industrial results
-
Hamdioui, S., Al-ars, Z., van de Goor, A.J., and Rodgers, M.: ' Linked faults in random-access-memories: concept, fault models, test algorithms and industrial results ', IEEE Trans. CAD Integr. Circuits Syst., 2004, 23, (5), p. 737-757
-
(2004)
IEEE Trans. CAD Integr. Circuits Syst.
, vol.23
, Issue.5
, pp. 737-757
-
-
Hamdioui, S.1
Al-Ars, Z.2
Van De Goor, A.J.3
Rodgers, M.4
-
28
-
-
0034503704
-
Impact of memory cell array bridges on the faulty behavior in embedded DRAMs
-
Al-Ars, Z., and van de Goor, Ad J.: ' Impact of memory cell array bridges on the faulty behavior in embedded DRAMs ', Records of Asian Test Symp., 2000, p. 282-289
-
(2000)
Records of Asian Test Symp.
, pp. 282-289
-
-
Al-Ars, Z.1
Van De Goor, A.J.2
-
29
-
-
84893689177
-
Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs
-
Al-ars, Z., and van de Goor, Ad J.: ' Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs ', Proc. Design Automation and Test in Europe, 2001, p. 496-503
-
(2001)
Proc. Design Automation and Test in Europe
, pp. 496-503
-
-
Al-Ars, Z.1
Van De Goor, A.J.2
-
30
-
-
48049116295
-
Defect oriented dynamic fault models for embedded SRAMs
-
Borri, S.: et al. ' Defect oriented dynamic fault models for embedded SRAMs ', Proc. European Test Symp., 2003, p. 23-28
-
(2003)
Proc. European Test Symp.
, pp. 23-28
-
-
Borri, S.1
-
31
-
-
84892556191
-
March SS: A test for all static simple RAM faults
-
Hamdioui, S., van de Goor, A.J., and Rodgers, M.: ' March SS: a test for all static simple RAM faults ', Proc. IEEE International Workshop on Memory Technology, Design, and Testing, 2002, p. 95-100
-
(2002)
Proc. IEEE International Workshop on Memory Technology, Design, and Testing
, pp. 95-100
-
-
Hamdioui, S.1
Van De Goor, A.J.2
Rodgers, M.3
-
33
-
-
0030385618
-
Detecting delay faults by very-low-voltage testing
-
Chang, J.Y-Y., and McCluskey, E.J.: ' Detecting delay faults by very-low-voltage testing ', Proc. Int. Test Conf., 1996, p. 367-376
-
(1996)
Proc. Int. Test Conf.
, pp. 367-376
-
-
Chang, J.Y.-Y.1
McCluskey, E.J.2
-
34
-
-
18144415503
-
Systematic defects in deep-submicron technologies
-
Kruseman, B.: et al. ' Systematic defects in deep-submicron technologies ', Proc. Int. Test Conf., 2002, p. 290-299
-
(2002)
Proc. Int. Test Conf.
, pp. 290-299
-
-
Kruseman, B.1
-
35
-
-
33645512489
-
Memory testing under different stress conditions: An industrial evaluation
-
Majhi, A.K.: et al. ' Memory testing under different stress conditions: an industrial evaluation ', Proc. Design, Automation and Test in Europe (DATE), 2005, p. 438-443
-
(2005)
Proc. Design, Automation and Test in Europe (DATE)
, pp. 438-443
-
-
Majhi, A.K.1
-
36
-
-
3142664872
-
New test methodology for resistive open defect detection in memory address decoders
-
Azimane, M., and Majhi, A.K.: ' New test methodology for resistive open defect detection in memory address decoders ', Proc. IEEE VLSI Test Symp., 2004, p. 123-128
-
(2004)
Proc. IEEE VLSI Test Symp.
, pp. 123-128
-
-
Azimane, M.1
Majhi, A.K.2
-
37
-
-
18144430666
-
Detecting faults in peripheral circuits and an evaluation of SRAM tests
-
USA, October
-
van de Goor, A.J., and Hamdioui, S.: ' Detecting faults in peripheral circuits and an evaluation of SRAM tests ', Proc. IEEE Int. Test Conf., USA, October 2004, p. 114-134
-
(2004)
Proc. IEEE Int. Test Conf.
, pp. 114-134
-
-
Van De Goor, A.J.1
Hamdioui, S.2
-
38
-
-
84948672443
-
Random testing of multi-port static random access memories
-
Karaimi, F., Meyer, F.J., and Lombardi, F.: ' Random testing of multi-port static random access memories ', Proc. IEEE Int. Workshop on Memory Technology, Design, and Testing, 2002, p. 101-106
-
(2002)
Proc. IEEE Int. Workshop on Memory Technology, Design, and Testing
, pp. 101-106
-
-
Karaimi, F.1
Meyer, F.J.2
Lombardi, F.3
-
39
-
-
0032312595
-
Detection of CMOS address decoder open faults with March and pseudo random memory tests
-
Otterstedt, J., Niggemeyer, D., and Williams, T.W.: ' Detection of CMOS address decoder open faults with March and pseudo random memory tests ', Proc. Int. Test Conf., 1998, p. 53-62
-
(1998)
Proc. Int. Test Conf.
, pp. 53-62
-
-
Otterstedt, J.1
Niggemeyer, D.2
Williams, T.W.3
-
40
-
-
0031382116
-
The implementation of pseudo-random memory tests on commercial memory testers
-
van de Goor, A.J., and Lin, M.: ' The implementation of pseudo-random memory tests on commercial memory testers ', Proc. IEEE Int. Test Conf., 1997, p. 226-235
-
(1997)
Proc. IEEE Int. Test Conf.
, pp. 226-235
-
-
Van De Goor, A.J.1
Lin, M.2
-
41
-
-
0035373085
-
Test challenges in nanometer technologies
-
Kundu, S.: et al. ' Test challenges in nanometer technologies ', J. Electron. Test. Theory Appl., 2001, 17, (3/4), p. 209-218
-
(2001)
J. Electron. Test. Theory Appl.
, vol.17
, Issue.3-4
, pp. 209-218
-
-
Kundu, S.1
-
42
-
-
3142719164
-
March iC-: An improved version of March C- for ADOFs detection
-
Dilillo, L.: et al. ' March iC-: an improved version of March C- for ADOFs detection ', Proc. IEEE VLSI Test Symp., 2004, p. 129-134
-
(2004)
Proc. IEEE VLSI Test Symp.
, pp. 129-134
-
-
Dilillo, L.1
-
43
-
-
0035701537
-
Tests for resistive and capacitive defects in address decoders
-
Klaus, M., and van de Goor, Ad.J.: ' Tests for resistive and capacitive defects in address decoders ', Proc. Asian Test Symp., 2001, p. 31-36
-
(2001)
Proc. Asian Test Symp.
, pp. 31-36
-
-
Klaus, M.1
Van De Goor, Ad.J.2
-
44
-
-
0034476391
-
Test method evaluation experiments & Data
-
Nigh, P., and Gattiker, A.: ' Test method evaluation experiments & Data ', Proc. IEEE Int. Test Conf., 2000, p. 454-463
-
(2000)
Proc. IEEE Int. Test Conf.
, pp. 454-463
-
-
Nigh, P.1
Gattiker, A.2
|