Detecting faults in the peripheral circuits and an evaluation of SRAM tests

Proceedings - International Test Conference

Volumn , Issue , 2004, Pages 114-123

  Van De Goor, Ad J ^a   Hamdioui, Said ^a,b   Wadsworth, Rob ^c  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b NXP SEMICONDUCTORS   (Netherlands)

^c ST Microlelctronics   (United States)

Author keywords

Address directions; Data backgrounds; Fault coverage; March tests; Peripheral circuit faults

Indexed keywords

ALGORITHMS; DATA REDUCTION; ELECTRIC FAULT CURRENTS; ELECTRIC WIRE; MATHEMATICAL MODELS; STATIC RANDOM ACCESS STORAGE;

ADDRESS DIRECTIONS; DATA-BACKGROUNDS; FAULT COVERAGE; MARCH TESTS; PERIPHERAL CIRCUIT FAULTS;

INTEGRATED CIRCUIT TESTING;

EID: 18144430666     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (29)

1. P. Nigh and A. Gattiker, 'Test Method Evaluation Experiments & Data'. In Proc. of the IEEE Int. Test Conf., 2000, pp.454-463
2. S. Kundu et al., 'Test Challenges in Nanometer Technologies', Journal of Electronic Testing: Theory and Applications, Vol. 17, No. 3/4, June/August 2001, pp. 209-218
3. A.D. Sathe et al., 'Analog Macromodeling of Capacitive Coupling Faults in Digital Circuit Interconnects'. In Proc. of the IEEE Int. Test Conf., 2002, pp.375-383
4. R.D. Adams and E.S. Cooley, "False Write Through and Un-Restored Write Electrical Level Faults Models for SRAMs", In Proc. of IEEE Int. Workshop on Memory Technology, Design and Test, pp. 21-32, 1997.
5. R. Nair et al., 'Efficient Algorithms for Testing Semiconductor Random-Access Memories', IEEE Trans, on Comp., C-27(6), 1978, pp. 572-576
6. D.S. Suk and S.M. Reddy, 'A March Test for Functional Faults in Semiconductor Random Access Memories', IEEE Trans. on Comp., C-30(12), 1981, pp. 982-982
7. M. Marinescu, 'Simple and Efficient Algorithms for Functional RAM Testing', In Proc. IEEE Int. Test Conf., 1982, pp. 236-239
8. M.S. Abadir and J.K. Reghbati, 'Functional Testing of Semi-conductor Random Access Memories', ACM Computing Surveys, 15(3), 1983, pp. 175-198
9. R. Dekker et al., 'Fault Modeling and Test Algorithm Development for Static Random Access Memories'. In Proc. of the IEEE Int. Test Conf. (ITC' 1988), 1988, pp.343-352
10. A.J. van de Goor, 'Testing Semiconductor Memories: Theory and Practice', ComTex Publishing, Gouda, The Netherlands, 1998; ISBN 90-804276-1-6. http://ce.et.tudelf.nl/~vdgoor/
11. R.D. Adams, 'High Performance Memory Testing', Kluwer Academic Publishers, Norwell, MA, USA, 2003
12. S. Hamdioui, 'Testing Static Random Access Memories: Defects, Fault Models and Test Patterns', Kluwer Academic Publishers, Boston, MA; ISBN 1-4020-7752-1, 2004
13. S.N.H. Goto and K. Iwasaki, 'Experiment fault analysis of 2Mb SRAM chips', Proc. of European Design and Test Conf., 1999, pp. 623-630
14. A. J. van de Goor and J. de Neef, 'Industrial Analysis of DRAM Tests', In Proc. Design Automation and Test in Europe, March 9-12, Munich, 1999, pp. 623-630
15. A. J. van de Goor and A. Paalvast, 'Industrial Evaluation of DRAM SIMM Tests', In Proc. IEEE Int. Test Conf., 2000, pp. 426-435
16. I. Schanstra and A.J. van de Goor, 'Industrial Evaluation of Stress Combinations for March Tests Applied to SRAMs', Proc. of the IEEE Int. Test Conf., 1999, pp. 983-992
17. th IEEE VLSI Test Symposium, Montreal, pp. 281-289
18. A.J. van de Goor and C.A. Verruijt, 'An Overview of Deterministic Functional RAM Chip Testing', ACM Computing Surveys, Vol. 22, No. 1, 1990, pp. 5-33
19. P. Mazumder, 'Parallel Testing of Parametric Faults in Three Dimensional Random-Access Memory', Proc. IEEE Int. Test Conf., 1988, pp. 933-941
20. A.J. van de Goor, 'Using March Tests to Test SRAMs', IEEE Design & Test of Computers, 1993, pp. 8-14
21. A.J. van de Goor et al., 'March LA: A Test for Linked Memory Faults', In Proc. European Design and Test Conference, 1997, pp. 627
22. A.J. van de Goor and G.N. Gaydadjiev, 'March LR: A Memory Test for Realistic Linked Faults', In Proc. IEEE VLSI Test Symposium, 1996, pp. 272-280
23. th IEEE VLSI Test Symposium, Monterey, CA, pp. 395-400
24. S. Hamdioui, A. J. van de Goor and M. Rodgers, 'March SS: A Test for All Static Simple RAM Faults', In Proc. of the IEEE Int. Workshop on Memory Technology, Design and Testing, Bendor, France, pp. 95-100
25. S. Hamdioui, Z. Al-Ars, A. J. van de Goor and M. Rodgers, 'Linked Faults in Random Access Memories: Concept, Fault Models, Test Algorithms and Industrial Results", In IEEE Trans, on Computer Aided Design of Integrated Circuits and Systems, Vol. 23, No. 5, pp. 195-205, May 2004.
26. A.J. van de Goor and G.N. Gaydadjiev, 'March U: A Test for Unlinked Memory Faults', IEE Proceedings Circuits, Devices and Systems; Vol. 144, No. 3, June 1997, pp. 155-160
27. J.H. de Jonge and A.J. Smeulders, 'Moving Inversion Test Pattern is Thorough, Yet Speedy', Computer Design, May 1976, pp. 169-173
28. B. Nadeau-Dostie et al., 'Serial Interfacing for Embedded-Memory Testing', IEEE Design & Test of Comp., Vol. 7, No. 2, 1990, pp. 52-63
29. M. Klaus and A. J. van de Goor, 'Tests for Resistive and Capacitive Defects in Address Decoders', In Proc. of the Tenth Asian Test Symposium (ATS'01), Kyoto, Japan, 2001, pp. 31-36