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Volumn 52, Issue 3, 2003, Pages 293-309

Static and dynamic behavior of memory cell array spot defects in embedded drams

Author keywords

Defect simulation; Dynamic faulty behavior; Embedded DRAM; Fault primitives; Functional fault models; Spot defects

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER SIMULATION; INTEGRATED CIRCUIT MANUFACTURE; STORAGE ALLOCATION (COMPUTER);

EID: 0037340134     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2003.1183945     Document Type: Article
Times cited : (28)

References (14)
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  • 3
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    • Schanstra, I.1    Van de Goor, A.J.2
  • 7
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    • Functional memory faults: A formal notation and a taxonomy
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  • 8
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    • A realistic fault model and test algorithms for static random access memories
    • June
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  • 10
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    • Carafe: An inductive fault analysis tool for CMOS VLSI circuits
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  • 11
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    • The behavior and testing implications of CMOS IC logic gate open circuits
    • C.L. Henderson, J.M. Soden, and C.F. Hawkins, "The Behavior and Testing Implications of CMOS IC Logic Gate Open Circuits," Proc. IEEE Int'l Test Conf., pp. 302-310, 1991.
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    • Henderson, C.L.1    Soden, J.M.2    Hawkins, C.F.3
  • 13
    • 84893689177 scopus 로고    scopus 로고
    • Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs
    • Z. Al-Ars and A.J. van de Goor, "Static and Dynamic Behavior of Memory Cell Array Opens and Shorts in Embedded DRAMs," Proc. Design, Automation and Test in Europe, pp. 496-503, 2001.
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    • Impact of memory cell array bridges on the faulty behavior in embedded DRAMs
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.