-
2
-
-
3142664872
-
New test methodology for resistive open defect detection in memory address decoders
-
[Azimane 04], April
-
[Azimane 04] M. Azimane and A. K. Majhi, "New Test Methodology for Resistive Open Defect Detection in Memory Address Decoders", Proc. VLSI Test Symposium, April 2004, pp. 123-128.
-
(2004)
Proc. VLSI Test Symposium
, pp. 123-128
-
-
Azimane, M.1
Majhi, A.K.2
-
3
-
-
48049116295
-
Defect-oriented dynamic fault models for embedded-SRAMs
-
[Borri 03]
-
[Borri 03] S. Borri, et. al., "Defect-Oriented Dynamic Fault Models for Embedded-SRAMs", Proc. of European Test Workshop, 2003, pp. 23-28.
-
(2003)
Proc. of European Test Workshop
, pp. 23-28
-
-
Borri, S.1
-
4
-
-
0030385618
-
Detecting delay flaws by very-low-voltage testing
-
[Chang 96], Oct
-
[Chang 96] J. T.-Y. Chang and E. J. McCluskey, "Detecting Delay Flaws by Very-Low-Voltage Testing", Proc. Int'l Test Conference, Oct 1996, pp. 367-376.
-
(1996)
Proc. Int'l Test Conference
, pp. 367-376
-
-
Chang, J.T.-Y.1
McCluskey, E.J.2
-
5
-
-
3142723471
-
The pros and cons of very-low-voltage testing: An analysis based on resistive bridging faults
-
[Engelke 04], April
-
[Engelke 04] P. Engelke, et.al., "The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults", Proc. VLSI Test Symp., April 2004, pp. 171-178.
-
(2004)
Proc. VLSI Test Symp.
, pp. 171-178
-
-
Engelke, P.1
-
6
-
-
0003784677
-
-
[vdGoor 98], COMTEX Publishing, Gouda, The Netherlands
-
[vdGoor 98] A. J. van de Goor, "Testing Semiconductor Memories, Theory and Practice", COMTEX Publishing, Gouda, The Netherlands, 1998.
-
(1998)
Testing Semiconductor Memories, Theory and Practice
-
-
Van De Goor, A.J.1
-
7
-
-
10044230601
-
The state-of-art and future trends in testing embedded memories
-
[Hamdioui 04], Aug.
-
[Hamdioui 04] S. Hamdioui, G. Gayadadjiev and A. J. van de Goor, "The State-of-art and Future Trends in Testing Embedded Memories", Int'l Workshop on Memory Technology, Design and Testing, Aug. 2004, pp. 54-59.
-
(2004)
Int'l Workshop on Memory Technology, Design and Testing
, pp. 54-59
-
-
Hamdioui, S.1
Gayadadjiev, G.2
Van De Goor, A.J.3
-
8
-
-
0035684844
-
Testing for resistive opens and stuck opens
-
[James 01], Oct.
-
[James 01] C. M. James, C. W. Tseng and E. J. McCluskey, "Testing for Resistive Opens and Stuck Opens", Proc. Int'l Test Conference, Oct. 2001, pp. 1049-1058.
-
(2001)
Proc. Int'l Test Conference
, pp. 1049-1058
-
-
James, C.M.1
Tseng, C.W.2
McCluskey, E.J.3
-
9
-
-
0036445141
-
Comparison of Iddq testing and very-low voltage testing
-
[Kruseman 02], Oct.
-
[Kruseman 02] B. Kruseman, S. van den Oetelaar and J. Rius, "Comparison of Iddq Testing and Very-Low Voltage Testing", Proc. Int'l Test Conference, Oct. 2002, pp. 964-973.
-
(2002)
Proc. Int'l Test Conference
, pp. 964-973
-
-
Kruseman, B.1
Van Den Oetelaar, S.2
Rius, J.3
-
10
-
-
18144415503
-
Systematic defects in deep sub-micron technologies
-
[Kruseman 04], Oct.
-
[Kruseman 04] B. Kruseman, A. Majhi, C. Hora, S. Eichenberger and J. Meirlevede, "Systematic Defects in Deep Sub-Micron Technologies", Proc. Int'l Test Conference, Oct. 2004.
-
(2004)
Proc. Int'l Test Conference
-
-
Kruseman, B.1
Majhi, A.2
Hora, C.3
Eichenberger, S.4
Meirlevede, J.5
-
11
-
-
0032314506
-
High volume microprocessor test escapes, an analysis of defects our tests are missing
-
[Needham 98], Oct
-
[Needham 98] W. Needham, C. Prunty and E. H. Yeoh, "High Volume Microprocessor Test Escapes, An Analysis of Defects Our Tests are Missing", Proc. Int'l Test Conference, Oct 1998, pp. 25-34.
-
(1998)
Proc. Int'l Test Conference
, pp. 25-34
-
-
Needham, W.1
Prunty, C.2
Yeoh, E.H.3
-
12
-
-
0033352919
-
Industrial evaluation of stress combinations for march tests applied to SRAMs
-
[Schanstra 99], Oct
-
[Schanstra 99] I. Schantra and Ad. J. van de Goor, "Industrial Evaluation of Stress Combinations for March Tests applied to SRAMs", Proc. Int'l Test Conference, Oct 1999, pp. 983-992.
-
(1999)
Proc. Int'l Test Conference
, pp. 983-992
-
-
Schantra, I.1
Van De Goor, A.J.2
-
13
-
-
0022201294
-
Inductive fault analysis of MOS integrated circuits
-
[Shen 85], Dec
-
[Shen 85] J. P. Shen, W. Maly and F. J. Ferguson, "Inductive Fault Analysis of MOS Integrated Circuits", IEEE Design & Test of Computers, vol. 2, no. 6, pp. 13-36, Dec 1985.
-
(1985)
IEEE Design & Test of Computers
, vol.2
, Issue.6
, pp. 13-36
-
-
Shen, J.P.1
Maly, W.2
Ferguson, F.J.3
-
14
-
-
0019659681
-
Defect level as a function of fault coverage
-
[Williams 81], Dec
-
[Williams 81] T. W. Williams and N. C. Brown, "Defect Level as a Function of Fault Coverage", IEEE Trans. On Computers, vol. C-30, pp. 987-988, Dec 1981.
-
(1981)
IEEE Trans. on Computers
, vol.C-30
, pp. 987-988
-
-
Williams, T.W.1
Brown, N.C.2
|