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Volumn , Issue , 1997, Pages 226-235

Implementation of pseudo-random memory tests on commercial memory testers

Author keywords

[No Author keywords available]

Indexed keywords

PROBABILITY; RANDOM ACCESS STORAGE;

EID: 0031382116     PISSN: 10893539     EISSN: None     Source Type: None    
DOI: 10.1109/TEST.1997.639618     Document Type: Conference Paper
Times cited : (3)

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    • R. Dekker Fault Modeling and Test Algorithm Development for Static Random Access Memories IEEE Trans. on Computers C-9 3 567 572 1990
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    • Fuentes, A.1
  • 5
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    • Automatic Computation of Test Length for Pseudo-Random Memory Tests
    • A.. J. van de Goor Automatic Computation of Test Length for Pseudo-Random Memory Tests Records of the 1995 IEEE Int. Workshop on Memory Tech. Design and Testing (MTDT'95) 55 61 Records of the 1995 IEEE Int. Workshop on Memory Tech. Design and Testing (MTDT'95) San Jose
    • van de Goor, A..J.1
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    • Testing Semiconductor Memories: Theory and Practice
    • John. Wiley & Sons U.K., Chichester
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    • (1991)
    • van de Goor, A.J.1
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    • Knuth, D.E.1
  • 9
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    • Is There Any Future for Deterministic Self-Test of Embedded RAMs?
    • A. Krasniewski G. Krzystof Is There Any Future for Deterministic Self-Test of Embedded RAMs? European Test Conf. 159 168 European Test Conf. 1993-March
    • (1993) , pp. 159-168
    • Krasniewski, A.1    Krzystof, G.2
  • 10
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    • Prog. Report
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    • Comments on an 'Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories'
    • R. Nair Comments on an 'Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories' IEEE Trans. on Computers C-34 2 110 116 1979
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.