Test challenges in nanometer technologies

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 17, Issue 3-4, 2001, Pages 209-218

  Kundu, Sandip ^a   Zachariah, Sujit T ^a   Sengupta, Sanjay ^a   Galivanche, Rajesh ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Circuit marginality testing; Defect based testing; Path delay testing; Process marginality testing

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; DEFECTS; ELECTRIC NETWORK ANALYSIS; INTEGRATED CIRCUIT TESTING; LEAKAGE CURRENTS; NANOTECHNOLOGY; STATISTICAL METHODS; THRESHOLD VOLTAGE;

CIRCUIT MARGINALITY TESTING; DEFECT BASED TESTING; PATH DELAY TESTING; PROCESS MARGINALITY TESTING; SOFTWARE PACKAGE EIFFEL; WEIGHTED CRITICAL AREA;

DIGITAL INTEGRATED CIRCUITS;

EID: 0035373085     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1012203009875     Document Type: Conference Paper

References (9)

1. On detecting bridges causing timing failures
2. Extraction simulation of realistic faults using inductive fault analysis
3. Intrinsic leakage in low power deep submicron CMOS ICs
4. Defect-based test: A key enabler for successful migration to structural test
5. On effective channel length in 0.1 μm MOSFETs
6. MOS scaling: Transistor challenges in the 21st century
7. A scalable and efficient methodology to extract two-node bridges from large industrial circuits
8. A novel algorithm for multi-node bridge analysis of large VLSI circuits
9. An efficient algorithm to extract two-node bridges