Simulation study of the dependence of submicron polysilicon thin-film transistor output characteristics on grain boundary position

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 44, Issue 12, 2005, Pages 8322-8328

  Walker, Philip M ^a   Uno, Shigeyasu ^b   Mizuta, Hiroshi ^c  

^a UNIVERSITY OF CAMBRIDGE   (United Kingdom)

^b CLAREMONT GRADUATE UNIVERSITY   (United States)

^c TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

Device simulation; Grain boundary; Polysilicon; Short channel effects; Thin film transistor

Indexed keywords

COMPUTER SIMULATION; ELECTRIC CONDUCTANCE; ENERGY GAP; GRAIN BOUNDARIES; INTEGRATED CIRCUIT MANUFACTURE; MATHEMATICAL MODELS; POLYSILICON;

DEVICE SIMULATION; SHORT CHANNEL EFFECTS;

THIN FILM TRANSISTORS;

EID: 31544441929     PISSN: 00214922     EISSN: 13474065     Source Type: Journal    
DOI: 10.1143/JJAP.44.8322     Document Type: Article

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