Modeling of laser-annealed polysilicon TFT characteristics

IEEE Electron Device Letters

Volumn 18, Issue 7, 1997, Pages 315-318

  Armstrong, G A ^a   Uppal, S ^a   Brotherton, S D ^b   Ayres, J R ^b  

^a QUEEN'S UNIVERSITY BELFAST   (United Kingdom)

^b PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; COMPUTER SIMULATION; CRYSTALLIZATION; CURRENT VOLTAGE CHARACTERISTICS; GRAIN BOUNDARIES; INTERFACES (MATERIALS); LASER APPLICATIONS; SEMICONDUCTOR DEVICE MANUFACTURE; SILICONES;

LASER ANNEALING;

THIN FILM TRANSISTORS;

EID: 0031185434     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.596923     Document Type: Article

References (16)

1. S. D. Brotherton, "Polycrystalline silicon thin-film transistors," Semicond. Sci. Technol., vol. 10, pp. 721-738, 1995.
2. G. Fortunate and P. Migliorato, "Determination of trap state density in polycrystalline silicon by field effect conductance," Appl. Phys. Lett., vol. 45, pp. 1025-1026, 1986.
3. M. Hack and A. G. Lewis, "Avalanche-induced effects in polysilicon thin-film transistors," IEEE Electron Device Lett., vol. 12, pp. 203-205, 1991.
4. T. S. Li and P. S. Lin, "On the pseudo-subthreshold characteristics of polycrystalline-silicon thin-film transistors with large grain size," IEEE Electron Device Lett., vol. 14, pp. 240-242, 1993.
5. G. Fortunato, "Analysis of hot-carrier effects, kink effect, and low-frequency noise in polycrystalline thin-film transistors," in Proc. POLYSE, Lake Garda, Italy, 1995, pp. 585-596.
6. M. Hack and J. G. Shaw, "Numerical simulation of amorphous and polycrystalline silicon thin-film transistors," in Ext. Abstr. 22nd Int. Conf. Solid-State Devices and Materials, Sendai, Japan, 1990, pp. 999-1003.
7. M. J. Edwards, S. D. Brotherton, J. R. Ayres, D. J. McCullough, and J. P. Gowers, "Laser crystallised polysilicon circuits for AMLCD's," in Proc. Asia Display'95, Hamamatsu, Japan, pp. 335-338.
8. R. Guerreri, P. Ciampolini, A. Gnudi, M. Rudan, and G. Baccarani, "Numerical simulation of polycrystalline silcon MOSFET's," IEEE Trans. Electron Devices, vol. ED-33, pp. 1201-1206, 1986.
9. ATLAS Software Manual, Silvaco International, Santa Clara, CA, 1994.
10. J. R. Ayres, "Characterization of trapping states in polycrystallinesilicon thin-film transistors by deep-level transient spectroscopy," J. Appl. Phys., vol. 74, pp. 1787-1792, 1993.
11. K. Yamaguchi, "A mobility model for carriers in the MOS inversion layer," IEEE Trans. Electron Devices, vol. ED-30, pp. 658-663, 1983.
12. P. V. Evans and S. F. Nelson, "Determination of grain boundary defect state densities from transport measurements," J. Appl. Phys., vol. 69. pp. 3605-3611, 1991.
13. C. A. Dimitriadis and D. H. Tassis, "Output characteristics of short-channel polycrystalline-silicon thin-film transistors," J. Appl. Phys., vol. 77, pp. 2177-2183, 1995.
14. C. Li, "A physical polysilicon thin-film transistor model for circuit simulation," Memo UCB/ERL m93/82, Electronics Research Laboratory, Univ. California, Berkeley, 1993.
15. M. Berger and Z. Chai, "Estimation of heat transfer in SOI-MOSFET's," IEEE Trans. Electron Devices, vol. 38, pp. 871-875, 1991.
16. L. J. McDaid et al., "Explanation for the negative differential resistance in SOI-MOSFET's," in Proc. ESSDERC89 Conf., 1989, pp. 885-888.