Evaluation of grain boundary trap states in polycrystalline-silicon thin-film transistors by mobility and capacitance measurements

Journal of Applied Physics

Volumn 91, Issue 7, 2002, Pages 4637-4645

  Ikeda, H ^a  

^a SONY CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BARRIER POTENTIAL; CAPACITANCE VOLTAGE CHARACTERISTIC; EFFECTIVE MOBILITIES; ERROR EFFECT; EVALUATING METHOD; EXCIMER LASER ANNEALING CRYSTALLIZATION; FIELD EFFECTS; GATE BIAS DEPENDENCE; GRAIN SIZE; INTERFACE TRAP STATE; POISSON'S EQUATION; POLY-SI TFTS; THEORETICAL BASIS; TRAP STATE; TRAP STATE DENSITY;

ACTIVATION ENERGY; CAPACITANCE MEASUREMENT; EXCIMER LASERS; GRAIN BOUNDARIES; POISSON EQUATION; SILICON; SURFACE POTENTIAL; THIN FILM TRANSISTORS;

INTERFACE STATES;

EID: 0036536114     PISSN: 00218979     EISSN: None     Source Type: Journal    
DOI: 10.1063/1.1454202     Document Type: Article

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