-
1
-
-
84954460028
-
Optimality and scalability study of existing placement algorithms
-
C. Chang, J. Cong, and M. Xie, "Optimality and scalability study of existing placement algorithms," in Proc. Asia South Pacific Design Automation Conference, pp. 621 - 627, 2003.
-
(2003)
Proc. Asia South Pacific Design Automation Conference
, pp. 621-627
-
-
Chang, C.1
Cong, J.2
Xie, M.3
-
2
-
-
0038716771
-
Optimality, scalability and stability study of partitioning and placement algorithms
-
J. Cong, M. Romesis, and M. Xie, "Optimality, scalability and stability study of partitioning and placement algorithms," in Proc. International Symposium on Physical Design, pp. 88 - 94, 2003.
-
(2003)
Proc. International Symposium on Physical Design
, pp. 88-94
-
-
Cong, J.1
Romesis, M.2
Xie, M.3
-
3
-
-
0024911063
-
Performance-driven placement of cell based IC's
-
M. Jackson and E. S. Kuh, "Performance-driven placement of cell based IC's," in Proc. Design Automation Conf, pp. 370-375, 1989.
-
(1989)
Proc. Design Automation Conf
, pp. 370-375
-
-
Jackson, M.1
Kuh, E.S.2
-
4
-
-
0027067732
-
RITUAL: A performance driven placement for small-cell ICs
-
A. Srinivasan, K. Chaudhary, and E. S. Kuh, "RITUAL: A performance driven placement for small-cell ICs," in Proc. Int. Conf. on Computer Aided Design, pp. 48-51, 1991.
-
(1991)
Proc. Int. Conf. on Computer Aided Design
, pp. 48-51
-
-
Srinivasan, A.1
Chaudhary, K.2
Kuh, E.S.3
-
5
-
-
0027316516
-
Prime: A timing-driven placement tool using a piecewise linear resistive network approach
-
T. Hamada, C. K. Cheng, and P. M. Chau, "Prime: a timing-driven placement tool using a piecewise linear resistive network approach," in Proc. Design Automation Conf, pp. 531-536, 1993.
-
(1993)
Proc. Design Automation Conf
, pp. 531-536
-
-
Hamada, T.1
Cheng, C.K.2
Chau, P.M.3
-
6
-
-
0021212391
-
Chip layout optimization using critical path weighting
-
A. E. Dunlop, V. D. Agrawal, D. N. Deutsch, M. F. Jukl, P. Kozak, and M. Wiesel, "Chip layout optimization using critical path weighting," in Proc. Design Automation Conf, pp. 133-136, 1984.
-
(1984)
Proc. Design Automation Conf
, pp. 133-136
-
-
Dunlop, A.E.1
Agrawal, V.D.2
Deutsch, D.N.3
Jukl, M.F.4
Kozak, P.5
Wiesel, M.6
-
7
-
-
0024716080
-
Generation of performance constraints for layout
-
R. Nair, C. L. Herman, P. Hauge, and E. J. Yoffa, "Generation of performance constraints for layout," IEEE Trans. on Computer-Aided Design, vol. 8, no. 8, pp. 860-874, 1989.
-
(1989)
IEEE Trans. on Computer-aided Design
, vol.8
, Issue.8
, pp. 860-874
-
-
Nair, R.1
Herman, C.L.2
Hauge, P.3
Yoffa, E.J.4
-
8
-
-
0026175786
-
An analytic net weighting approach for performance optimization in circuit placement
-
R. S. Tsay and J. Koehl, "An analytic net weighting approach for performance optimization in circuit placement," in Proc. Design Automation Conf, pp. 620-625, 1991.
-
(1991)
Proc. Design Automation Conf
, pp. 620-625
-
-
Tsay, R.S.1
Koehl, J.2
-
10
-
-
0029708441
-
Characterization and parameterized random generation of digital circuits
-
ACM Press
-
M. Mutton, J. P. Grossman, J. Rose, and D. Cornell, "Characterization and parameterized random generation of digital circuits," in Proc. Design Automation Conf, pp. 94-99, ACM Press, 1996.
-
(1996)
Proc. Design Automation Conf
, pp. 94-99
-
-
Mutton, M.1
Grossman, J.P.2
Rose, J.3
Cornell, D.4
-
11
-
-
0346237894
-
Synthetic benchmark circuits for timing-driven physical design applications
-
CSREA Press
-
P. Verplaetse, D. Stroobandt, and J. Van Campenhout, "Synthetic benchmark circuits for timing-driven physical design applications," in Proc. International Conference on VLSI, pp. 31-37, CSREA Press, 2002.
-
(2002)
Proc. International Conference on VLSI
, pp. 31-37
-
-
Verplaetse, P.1
Stroobandt, D.2
Van Campenhout, J.3
-
12
-
-
34748823693
-
The Transient Response of Damped Linear Networks
-
W. C. Elmore, "The Transient Response of Damped Linear Networks," Journal of Applied Physics, vol. 19, pp. 55 -63, 1948.
-
(1948)
Journal of Applied Physics
, vol.19
, pp. 55-63
-
-
Elmore, W.C.1
-
13
-
-
0002702472
-
Interconnect delay estimation models for synthesis and design planning
-
J. Cong, and D. Pan, "Interconnect delay estimation models for synthesis and design planning," in Asia Pacific Design Automation Conference, pp. 97-100, 1999.
-
(1999)
Asia Pacific Design Automation Conference
, pp. 97-100
-
-
Cong, J.1
Pan, D.2
-
14
-
-
0019896149
-
Timing Analysis of Computer Hardware
-
R. Hitchcock, G. Smith, and D. Cheng, "Timing Analysis of Computer Hardware," IBM J. Res. Develop., vol. 26, pp. 100-108, 1982.
-
(1982)
IBM J. Res. Develop.
, vol.26
, pp. 100-108
-
-
Hitchcock, R.1
Smith, G.2
Cheng, D.3
-
16
-
-
0033723218
-
Timing-driven placement for FPGAs
-
ACM Press
-
A. Marquardt, V. Betz, and J. Rose, "Timing-driven placement for FPGAs," in Proc. of the ACM/SIGDA international symposium on Field programmable gate arrays, pp. 203-213, ACM Press, 2000.
-
(2000)
Proc. of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays
, pp. 203-213
-
-
Marquardt, A.1
Betz, V.2
Rose, J.3
-
17
-
-
84855625596
-
-
http://cadlab.cs.ucla.edu/̃pubbench/tpeko.htm.
-
-
-
-
20
-
-
84855635206
-
-
http://www.eecg.toronto.edu/̃vaghn/vpr/vpr.html.
-
-
-
-
21
-
-
0036907067
-
A novel net weighting algorithm for timing-driven placement
-
T. Kong, "A novel net weighting algorithm for timing-driven placement," in Proc. Intl. Conf. on Computer-Aided Design, pp. 172 - 176, 2002.
-
(2002)
Proc. Intl. Conf. on Computer-aided Design
, pp. 172-176
-
-
Kong, T.1
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