A study of tighter lower bounds in LP relaxation based placement

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2005, Pages 498-502

  Wang, Qingzhou ^a   Jariwala, Devang ^a   Lillis, John ^a  

^a 1120 Science and Engineering Offices   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; ELECTRIC WIRE; FIELD PROGRAMMABLE GATE ARRAYS;

CELL DISTRIBUTION; CELL-BASED DESIGNS; WIRE-LENGTH;

LINEAR PROGRAMMING;

EID: 29244482316     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1057661.1057780     Document Type: Conference Paper

References (9)

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