An efficient approach to SoC wrapper design, TAM configuration and test scheduling

Proceedings of the European Test Workshop

Volumn 2003-January, Issue , 2003, Pages 51-56

  Pouget, J ^a   Larsson, E ^a   Peng, Z ^a   Flottes, M L ^b   Rouzeyre, B ^b  

^a LINKÖPING UNIVERSITY   (Sweden)

^b LIRMM   (France)

Author keywords

Built in self test; Design methodology; Embedded system; Energy consumption; Job shop scheduling; Laboratories; Power dissipation; Power system interconnection; System testing; System on a chip

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BUILT-IN SELF TEST; DESIGN; ELECTRIC LOSSES; ELECTRIC POWER SYSTEM INTERCONNECTION; EMBEDDED SYSTEMS; ENERGY DISSIPATION; ENERGY UTILIZATION; INTEGRATED CIRCUIT INTERCONNECTS; INTEGRATED CIRCUIT TESTING; JOB SHOP SCHEDULING; LABORATORIES; MICROPROCESSOR CHIPS; OPTIMIZATION; PROGRAMMABLE LOGIC CONTROLLERS; SCHEDULING; SEMICONDUCTOR DEVICE MANUFACTURE; SYSTEM-ON-CHIP;

DESIGN METHODOLOGY; POWER SYSTEM INTERCONNECTION; PRECEDENCE CONSTRAINTS; PROPOSED ARCHITECTURES; SYSTEM ON A CHIP; SYSTEM TESTING; SYSTEM-ON-CHIP TESTING; TEST ACCESS MECHANISM;

INTEGRATED CIRCUIT DESIGN;

EID: 84942925785     PISSN: 15301877     EISSN: 15581780     Source Type: Conference Proceeding    
DOI: 10.1109/ETW.2003.1231668     Document Type: Conference Paper

References (20)

1. http://www.extra.research.philips.com/itc02socbenchm/format.html
2. K. Chakrabarty: " Test Scheduling For Core Based Systems",ICCAD'99, pp. 391-394, 1999.
3. K. Chakrabarty, V. Iyengar, E. J. Marinissen: "Test wrapper and Test Access Mechanism Co-Optimization for System-on-Chip", ITC'01, pp. 1023-1032, 2001.
4. R. Chou, K. Saluja, V. Agrawal: "Scheduling Tests for VLSI Systems under Power Constraints", IEEE Trans. On VLSI Systems, Vol. 5, No. 2, pp. 175-185, 1997.
5. E. Cota, L. Caro, A. Orailoglu, M. Lubaszewski: "Test Planning and Design Space Exploration in a Core Base Environment", DATE'02, pp. 478-485, 2002.
6. M.L. Flottes, J. Pouget, B. Rouzeyre: "Sessionless Test Scheme: Power-constrained Test Scheduling for System-on-a-Chip", VLSI-SoC'01, pp. 105-110, 2001.
7. M.R. Garey, D. Jonhson: "Computers and Intractability: guide to the theory of NP-completeness", W.H. Freeman and Company, San Francisco, 1979.
8. P. Harrod: "Testing reusable IP - A Case Study", ITC'99, pp. 493-498, 1999.
9. Y. Huang, S.M. Reddy, W.T. Cheng, P. Reuter, N. Mukherjee, C.C. Tsai, O. Samman, Y. Zaidan: "Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on Bin Packing Algorithm", ITC'02, pp. 74-82, 2002.
10. V.Iyengar, K. Chakrabarty: "Precedence-Based, Preemptive and Power-Constrained Test Scheduling for System-on-a-Chip", VLSI-SoC'01, pp. 368-374, 2001.
11. V. Iyengar, K. Chakrabarty, E. J. Marinissen: "Efficient Wrapper/TAM Co-Optimization for Large SOCs", DATE'02, pp. 491-498, 2002.
12. V. Iyengar, K. Chakrabarty, E. J. Marinissen: "On Using Rectangle Packing for SoC Wrapper/TAM co-optimization", VTS'02, pp. 253-258, 2002.
13. E. J. Marinissen, S. K. Goel and M. Lousberg: "Wrapper Design for Embedded Core Test", ITC'00, pp. 911-920, 2000.
14. E. J. Marinissen, V. Iyengar, K. Chakrabarty: "A set of Benchmarks for Modular Testing of SoCs", ITC'02, pp. 519-528, 2002.
15. V. Muresan, X. Wang, M. Vladutiu, V. Muresan: "A comparison of classical Scheduling Approaches in Power-Constrained Block-Test Scheduling", ITC'00, pp. 882-891, 2000.
16. Nicola Nicolici, B.M. Al-Hashimi: "Power Conscious Test Synthesis and Scheduling for BIST RTL Data Paths", ATS'99, pp. 107-112.
17. M. Nourani and C. Papachristou: "An ILP Formulation to optimize Test Access Mechanism in System-on-Chip Testing", ITC'00, pp. 902-910, 2000.
18. Julien Pouget: "Embedded Test for System-On-Chips: Test Scheduling and Architectural Solutions", PhD Thesis, 2002. www.ida.liu.se/~g-julpo/
19. C.P. Ravikumar, A. Verma, G. Chandra: "A Polynomial-Time Algorithm for Power Constrained Testing of Core Based Systems", ATS'99, pp. 107-112.
20. Y. Zorian: "System-On-Chip Test Strategies", DAC'98, pp. 752-756.