SOC test time minimization under multiple constraints

Proceedings of the Asian Test Symposium

Volumn 2003-January, Issue , 2003, Pages 312-317

  Pouget, J ^a   Larsson, E ^a   Peng, Z ^a  

^a LINKÖPING UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DISTRIBUTED COMPUTER SYSTEMS; EMBEDDED SYSTEMS; INTEGRATED CIRCUIT TESTING; MICROPROCESSOR CHIPS; PROGRAMMABLE LOGIC CONTROLLERS;

CORE TESTING; MULTIPLE CONSTRAINT; MULTIPLE TEST; PRECEDENCE CONSTRAINTS; SOC (SYSTEM ON CHIP); TEST ACCESS MECHANISM; TEST APPLICATION TIME; TEST SCHEDULING;

SYSTEM-ON-CHIP;

EID: 3142766672     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ATS.2003.1250829     Document Type: Conference Paper

References (14)

1. E. Cota, L. Carro, M. Lubaszewski, and A. Orailoglu, "Test Planning and Design Space Exploration in a Core-based Environment", Proceedings of the Design, Automation and Test in Europe Conference (DATE), pp. 478-485, Paris, France, March 2002.
2. H-S Hsu, J-R Huang, K-L Cheng, C-W Wang, C-T Huang, and C-W Wu, "Test Scheduling and Test Access Architecture Optimization for System-on-Chip", Proceedings of IEEE Asian Test Symposium (ATS), pp. 411-416, Tamuning, Guam, USA, November 2002.
3. Y. Huang, S.M. Reddy, W-T Cheng, P. Reuter, N. Mukherjee, C-C Tsai, O. Samman, Y. Zaidan, "Optimal core wrapper width selection and SOC test scheduling based on 3-D bin packing algorithm", Proceedings IEEE of International Test Conference (ITC), pp. 74-82, Baltimore, MD, USA, October 2002.
4. V. Iyengar, K. Chakrabarty, and E. J. Marinissen, "Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip", Journal of Electronic Testing; Theory and Applications (JETTA), pp. 213-230, April 2002.
5. V. Iyengar K. Chakrabarty, and E. J. Marinissen, "Efficient Wrapper/TAM Co-Optimization for Large SOCs", Proceedings of Design and Test in Europe (DATE), pp. 491-498, Paris, France, March 2002.
6. V. Iyengar, K. Chakrabarty, and E. J. Marinissen, "On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization", Proceedings of IEEE VLSI Test Symposium (VTS), pp. 253-258, Monterey, California, USA, April 2002.
7. V. Iyengar, S. K. Goel, E. J. Marinissen and K. Chakrabarty, "Test Resource Optimization for Multi-Site Testing of SOCs under ATE Memory Depth Constraints", Proceedings of IEEE International Test Conference, pp. 1159-1168, Baltimore, MD, USA, October 2002.
8. V. Iyengar, K. Chakrabarty, M. D. Krasniewski, and G. N. Kuma, "Design and Optimization of Multi-level TAM Architectures for Hierarchical SOCs", Proceedings of IEEE VLSI Test Symposium (VTS), pp. 299-304, 2003.
9. S. K. Goel and E. J. Marinissen, "Cluster-Based Test Architecture Design for System-On-Chip, Proceedings of IEEE VLSI Test Symposium (VTS), pp. 259-264, Monterey, California, USA, April 2002.
10. S. K. Goel and E. J. Mariniseen, "Effective and efficient test architecture design for SOCs", Proceedings of IEEE International Test Conference, pp. 529-538, Baltimore, MD, USA, October 2002.
11. S. Koranne, "On Test Scheduling for Core-based. SOCs", Proceedings of International Conference on VLSI Design, pp 505-510, Bangalore, India, January 2002.
12. S. Koranne and V. Iyengar, "On the use of k - tuples for SoC test schedule representation", Proceedings of International Test Conference (ITC), pp. 539-548, Baltimore, MD, USA, October 2002.
13. E. J.Marinissen, R. Kapur, and Y. Zorian, "On Using IEEE P1500 SECT for Test Plug-n-play", Proceedings of IEEE International Test Conference (ITC), pp. 770-777, Atlantic City, NJ, USA, October 2000.
14. J. Pouget, E. Larsson, Z. Peng, M.-L. Flottes, B. Rouzeyre, "An Efficient Approach to SoC Wrapper Design, TAM configuration, and Test Scheduling", Proceedings of IEEE European Test Workshop (ETW), Maastricht, The Nederlands, May 2003.