An industrially effective environment for formal hardware verification

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 24, Issue 9, 2005, Pages 1381-1404

  Seger, Carl Johan H ^b   Jones, Robert B ^a,b,g   O'Leary, John W ^a,b   Melham, Tom ^c,h   Aagaard, Mark D ^a,d   Barrett, Clark ^e   Syme, Don ^f  

^a IEEE

^b INTEL CORPORATION   (United States)

^c UNIVERSITY OF OXFORD   (United Kingdom)

^d UNIVERSITY OF WATERLOO   (Canada)

^e POLYTECHNIC UNIVERSITY   (United States)

^f MICROSOFT RESEARCH   (United Kingdom)

^g ACM   (Japan)

^h BALLIOL COLLEGE   (United Kingdom)

Author keywords

BDDs; Formal verification; Model checking; Symbolic trajectory evaluation; Theorem proving

Indexed keywords

BDDS; FORMAL VERIFICATION; MODEL CHECKING; SYMBOLIC TRAJECTORY EVALUATION (STE);

ALGORITHMS; COMPUTER HARDWARE; COMPUTER HARDWARE DESCRIPTION LANGUAGES; EVALUATION; LINEAR PROGRAMMING; MATHEMATICAL MODELS; THEOREM PROVING;

FORMAL LOGIC;

EID: 27644588866     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.850814     Document Type: Article

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