A methodology for large-scale hardware verification

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1954, Issue , 2000, Pages 263-282

  Aagaard, Mark D ^a   Jones, Robert B ^a   Melham, Thomas F ^b   O’Leary, John W ^a   Seger, Carl Johan H ^a  

^a INTEL CORPORATION   (United States)

^b UNIVERSITY OF GLASGOW   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; COMPUTATIONAL LINGUISTICS; COMPUTER AIDED DESIGN; COMPUTER HARDWARE; DIGITAL ARITHMETIC; FORMAL LOGIC; FORMAL METHODS; FORMAL VERIFICATION; HARDWARE; MODEL CHECKING; SPECIFICATION LANGUAGES;

DATA PATHS; FLEXIBLE FRAMEWORK; HARDWARE VERIFICATION; HIGHER ORDER LOGIC; INDUSTRIAL TRIAL; LARGE SCALE VERIFICATION; PRECISION FLOATING POINT; VERIFICATION METHODOLOGY;

FUNCTIONAL PROGRAMMING;

EID: 84947227678     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: None     Document Type: Conference Paper

References (16)

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