Divider circuit verification with model checking and theorem proving

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1869, Issue , 2000, Pages 338-355

  Kaivola, Roope ^a   Aagaard, Mark D ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL ARITHMETIC; FORMAL VERIFICATION; MODEL CHECKING; TIMING CIRCUITS;

DIVIDER CIRCUITS; FLOATING-POINT DIVIDER; HARDWARE VERIFICATION; INDUSTRIAL SIZE; INTEGER ARITHMETIC; MODEL-CHECKING TECHNIQUES; SYMBOLIC TRAJECTORY EVALUATION; THEOREM PROVERS;

THEOREM PROVING;

EID: 84949236734     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-44659-1_21     Document Type: Conference Paper

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