Efficient modeling of memory arrays in symbolic ternary simulation

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1384, Issue , 1998, Pages 136-150

  Velev, Miroslav N ^a   Bryant, Randal E ^a,b  

^a Department of Electrical and Computer Engineering ^*  (United States)

^b Carnegie Mellon University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BEHAVIORAL RESEARCH; EMBEDDED SYSTEMS; MEMORY ARCHITECTURE; MODEL CHECKING;

BEHAVIORAL MODEL; MEMORY LOCATIONS; MEMORY MODELING; SOFTWARE INTERFACES; SYMBOLIC SIMULATION; SYMBOLIC TRAJECTORY EVALUATION; TRANSISTOR LEVEL; VERIFICATION TOOLS;

COMPUTER SOFTWARE;

EID: 84947917515     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/bfb0054169     Document Type: Conference Paper

References (11)

1. D.L. Beatty, R. E. Bryant, and C.-J. H. Seger, "Synchronous Circuit Verification by Symbolic Simulation: An Illustration" Sixth MIT Conference on Advanced Research in VLSI, 1990, pp. 98-112.
2. R.E. Bryant, "Symbolic Boolean Manipulation with Ordered Binary-Decision Diagrams" ACM Computing Serveys, Vol. 24, No. 3 (September 1992), pp. 293-318.
3. R.E. Bryant, D. E. Beatty, and C.-J. H. Seger, "Formal Hardware Verification by Symbolic Ternary Trajectory Evaluation," 28th Design Automation Conference, June 1991, pp. 297-402.
4. J.R. Butch, E. M. Clarke, K. L. McMillan, and D. L. Dill, "Sequential Circuit Verification Using Symbolic Model Checking" 27th Design Automation Conference, June 1990, pp. 46-51.
5. J.R. Burch, E. M. Clarke, and D. E. Long, "Representing Circuits More Efficiently in Symbolic Model Checking," 28th Design Automation Conference, June 1991, pp. 403-407.
6. J.R. Butch, and D. L. Dill, "Automated Verification of Pipelined Microprocessor Control" CAV '94, D. L. Dill, ed., LNCS 818, Springer-Verlag, June 1994, pp. 68-80.
7. A. Jain, "Formal Hardware Verification by Symbolic Trajectory Evaluation," Ph.D. thesis, Department of Electrical and Computer Engineering, Carnegie Mellon University, August 1997.
8. M. Pandey, "Formal Verification of Memory Arrays" Ph.D. thesis, School of Computer Science, Carnegie Mellon University, May 1997.
9. M. Pandey, and R. E. Bryant, "Exploiting Symmetry When Verifying Transistor-Level Circuits by Symbolic Trajectory Evaluation;" CAV '97, O. Grumberg, ed., LNCS 1254, Springer-Veflag, June 1997, pp. 244-255.
10. C.-J. H. Seger, and R. E. Bryant, "Formal Verification by Symbolic Evaluation of Partially-Ordered Trajectories," Formal Methods in System Design, Vol. 6, No. 2 (March 1995), pp. 147-190.
11. I. M. Velev, R. E. Bryant, and A. Jain, "Efficient Modeling of Memory Arrays in Symbolic Simulation "2 CAV '97, O. Grnmberg, ed., LNCS 1254, Springer-Verlag, June 1997, pp. 388-399.