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Volumn 2144, Issue , 2001, Pages 386-402

Using abstract specifications to verify powerPC™ custom memories by symbolic trajectory evaluation

Author keywords

[No Author keywords available]

Indexed keywords

MODEL CHECKING; ROBOTS; SPECIFICATIONS;

EID: 84947233560     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-44798-9_30     Document Type: Conference Paper
Times cited : (6)

References (12)
  • 4
    • 0031641691 scopus 로고    scopus 로고
    • Automatic Generation of Assertions for Formal Verification of PowerPC Microprocessor Arrays Using Symbolic Trajectory Evaluation
    • June
    • L.-C. Wang, M. S. Abadir, N. Krishnamurthy. “Automatic Generation of Assertions for Formal Verification of PowerPC Microprocessor Arrays Using Symbolic Trajectory Evaluation”. 35th ACM/IEEE DAC, June, 1998.
    • (1998) 35Th ACM/IEEE DAC
    • Wang, L.-C.1    Abadir, M.S.2    Krishnamurthy, N.3
  • 6
    • 0001510331 scopus 로고
    • Formal verification by symbolic evaluation of partially-ordered trajectories
    • March
    • C.-J. H. Seger and R. E. Bryant. “Formal verification by symbolic evaluation of partially-ordered trajectories”. Formal Methods in System Design, 6(2):147-189, March, 1995.
    • (1995) Formal Methods in System Design , vol.6 , Issue.2 , pp. 147-189
    • Seger, C.-J.H.1    Bryant, R.E.2
  • 8
    • 0022769976 scopus 로고
    • Graph-Based Algorithms for Boolean Function Manipulation
    • August
    • R. E. Bryant. “Graph-Based Algorithms for Boolean Function Manipulation”. IEEE Transactions on Computers, 35(8), August 1986.
    • (1986) IEEE Transactions on Computers , vol.35 , Issue.8
    • Bryant, R.E.1
  • 10
    • 0030398539 scopus 로고    scopus 로고
    • PowerPC array verification methodology using formal techniques
    • N. Ganguly, M. S. Abadir, M. Pandey. “PowerPC array verification methodology using formal techniques”. International Test Conference 1996, pp.857-864.
    • (1996) International Test Conference , pp. 857-864
    • Ganguly, N.1    Abadir, M.S.2    Pandey, M.3
  • 11
    • 0029720912 scopus 로고    scopus 로고
    • Formal Verification of PowerPC arrays using Symbolic Trajectory Evaluation
    • June
    • M. Pandey, R. Raimi, D. L. Beatty, R. E. Bryant. “Formal Verification of PowerPC arrays using Symbolic Trajectory Evaluation”. 33rd ACM/IEEE DAC, June 1996, pp.649-654.
    • (1996) 33Rd ACM/IEEE DAC , pp. 649-654
    • Pandey, M.1    Raimi, R.2    Beatty, D.L.3    Bryant, R.E.4
  • 12
    • 0030651836 scopus 로고    scopus 로고
    • Formal Verification of Content Addressable Memories using Symbolic Trajectory Evaluation
    • June
    • M. Pandey, R. Raimi, R. E. Bryant, M. S. Abadir. “Formal Verification of Content Addressable Memories using Symbolic Trajectory Evaluation”. 34th ACM/IEEE DAC, June 1997.
    • (1997) 34Th ACM/IEEE DAC
    • Pandey, M.1    Raimi, R.2    Bryant, R.E.3    Abadir, M.S.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.