Practical application of formal verification techniques on a frame mux/demux chip from nortel semiconductors

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1703, Issue , 1999, Pages 110-124

  Xu, Y ^a   Cerny, E ^b   Silburt, A ^a   Coady, A ^a   Liu, Y ^a   Pownall, P ^a  

^a NORTEL NETWORKS   (Canada)

^b UNIVERSITÉ DE MONTRÉAL   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN; HARDWARE; MODEL CHECKING; RECONFIGURABLE HARDWARE;

CIRCUIT STRUCTURES; CLASSICAL SIMULATION; DESIGN ERRORS; MODEL REDUCTION; MUX/DEMUX CHIPS; RANDOM SIMULATION; REDUCTION ALGORITHMS; VERIFICATION TECHNIQUES;

FORMAL VERIFICATION;

EID: 84958633310     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-48153-2_10     Document Type: Conference Paper

References (15)

1. A. Silburt Invited Lecture: ASIC/System Hardware Verification at Nortel: A View from the Trenches. Proceeding of the 9th IFIP WG10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods (CHARME'97), October,1997, Montreal Canada.
2. A.J. Camilleri. A role for Theorem Proving in Multi-processor Design. Proceeding of the 10th International Conference on Computer Aided Verification (CAV’98),Vancouver, BC Canada, June/July 1998.
3. D.L. Dill. What’s Between Simulation and Formal Verification. Proceeding of the 35th Design Automation Conference (DAC’98), San Francisco, CA, USA, June 1998
4. FormalCheck User’s Guide. Bell labs Design Automation, Lucent Technologies, V1.1, 1997
5. K. L. McMillan. Symbolic model checking - an approach to the state explosion problem. Ph.D. thesis, SCS, Carnegie Mellon University, 1992. (See also Cadence Design Systems, Inc. www pages.)
6. In Design Automation, Inc., “Whitebox verification,” http://www.0-in.com/tools.
7. In Design Automation, Inc., “0-In search,” http://www.0-in.com/tools.
8. System Science, Inc. (Synopsys, Inc.), “The VERA verification system,” http://www.systems.com/products/vera.
9. TransEDA, Inc., “VeriSure- Verilog code coverage tool,” http://www.transeda.com/products.
10. Lucent Technologies,”FormalCheck model checker,” http:/www.bell-labs.com/org/blda/product.formal.html.
11. P. Bratley, B.L. Fox, L.E. Schrage, A Guide to Simulation, 2nd Edition, Springer- Verlag, New York, 1986.
12. L. Devroye, Non-Uniform Random Variate Generation, Springer-Verlag, New York, 1986.
13. CheckOff User Guide, Siemens Nixdorf Informations Systemen AG & Abstract Hardware Limited, January, 1996.
14. Lambda user’s manual, Abstract Hardware limited, 1995.
15. Verisity Design, Inc. Specman Data Sheet, http://www.verisity.com.