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Volumn 1427 LNCS, Issue , 1998, Pages 110-121

Verification of an implementation of tomasulo's algorithm by compositional model checking

Author keywords

[No Author keywords available]

Indexed keywords

COMPOSITIONAL MODELS; FINITE-STATE; OUT OF ORDER; PROCESSING UNITS; PROOF SYSTEM; REFINEMENT MAPS; TOMASULO; COMPOSITIONAL MODELING; FINITE STATE METHODS; HIGHER-ORDER;

EID: 84863924303     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: None     Document Type: Conference Paper
Times cited : (93)

References (17)
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    • Burch, J.R.1    Dill, D.L.2
  • 6
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    • Verifying out-of-order executions
    • D. Probst, editor Chapman & Hall To appear
    • W. Damm and A. Pnueli. Verifying out-of-order executions. In D. Probst, editor, CHARME '97. Chapman & Hall, 1997. To appear.
    • (1997) CHARME '97
    • Damm, W.1    Pnueli, A.2
  • 8
    • 0030211668 scopus 로고    scopus 로고
    • Better verification through symmetry
    • C.N. Ip and D.L. Dill. Better verification through symmetry. Formal Methods in System Design, 9(1-2):41-75, Aug. 1996. (Pubitemid 126708456)
    • (1996) Formal Methods in System Design , vol.9 , Issue.1-2 , pp. 41-75
    • Norris Ip, C.1    Dill, D.L.2
  • 9
    • 84863948406 scopus 로고    scopus 로고
    • Verifying nondeterministic implementations of deterministic systems
    • Formal Methods in Computer-Aided Design
    • A. Jain, K. Nelson, and R. E. Bryant. Verifying nondeterministic implementations of deterministic systems. In Formal Methods in Computer-Aided Design (FMCAD '96), pages 109-25, 1996. (Pubitemid 126149752)
    • (1996) Lecture Notes in Computer Science , Issue.1166 , pp. 109-125
    • Jain, A.1    Nelson, K.2    Bryant, R.E.3
  • 10
    • 0029219688 scopus 로고
    • Verity - A formal verification program for custom CMOS circuits
    • Jan.-Mar.
    • A. Kuehlmann, A. Srinivasan, and D. P. LaPotin. Verity - a formal verification program for custom CMOS circuits. IBM J. of Research and Development, 39(1-2):149-65, Jan.-Mar. 1995.
    • (1995) IBM J. of Research and Development , vol.39 , Issue.1-2 , pp. 149-165
    • Kuehlmann, A.1    Srinivasan, A.2    LaPotin, D.P.3
  • 12
    • 0030685021 scopus 로고    scopus 로고
    • The alpha 21264: A 500 mhz out-of-order execution microprocessor
    • D. Leibholz and R. Razdan. The alpha 21264: a 500 mhz out-of-order execution microprocessor. In Digest of Papers, COMPCON Spring 97, pages 28-36, 1997.
    • (1997) Digest of Papers, COMPCON Spring 97 , pp. 28-36
    • Leibholz, D.1    Razdan, R.2
  • 14
    • 84947418436 scopus 로고    scopus 로고
    • A compositional rule for hardware design refinement
    • Computer Aided Verification
    • K. L. McMillan. A compositional rule for hardware design refinement. In Computer Aided Verification (CAV'97), pages 24-35, 1997. (Pubitemid 127088962)
    • (1997) Lecture Notes in Computer Science , Issue.1254 , pp. 24-35
    • McMillan, K.L.1
  • 15
    • 0016951439 scopus 로고
    • Verifying properties of parallel programs
    • May
    • S. Owicki and D. Gries. Verifying properties of parallel programs. Comm. ACM, 19(5):279-85, May 1976.
    • (1976) Comm. ACM , vol.19 , Issue.5 , pp. 279-285
    • Owicki, S.1    Gries, D.2
  • 17
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    • An efficient algorithm for exploiting multiple arithmetic units
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    • R. M. Tomasulo. An efficient algorithm for exploiting multiple arithmetic units. IBM J. of Research and Development', 11(1):25-33, Jan. 1967.
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    • Tomasulo, R.M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.