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Volumn , Issue , 2003, Pages 1-6

High level formal verification of next-generation microprocessors

Author keywords

Formal Property Verification

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER DEBUGGING; COMPUTER SIMULATION; DIGITAL ARITHMETIC; DIGITAL STORAGE; MICROPROCESSOR CHIPS;

EID: 0043092223     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/775832.775834     Document Type: Conference Paper
Times cited : (40)

References (12)
  • 1
    • 0042196503 scopus 로고    scopus 로고
    • Applications of hierarchical verification in model checking
    • published in CHARM 2001 proceedings
    • R. Beers, R. Ghughal, and M. Aagaard, "Applications of Hierarchical Verification in Model Checking." FMCAD 2000 (published in CHARM 2001 proceedings).
    • (2000) FMCAD
    • Beers, R.1    Ghughal, R.2    Aagaard, M.3
  • 5
    • 0005599065 scopus 로고    scopus 로고
    • Symbolic trajectory evaluation
    • T. Kropf, editor, chapter 1. Springer Verlag; New York
    • S. Hazelhurst and C-J Seger, "Symbolic trajectory evaluation." In T. Kropf, editor, Formal Hardware Verification, chapter 1, pagers 3-78. Springer Verlag; New York, 1997.
    • (1997) Formal Hardware Verification , pp. 3-78
    • Hazelhurst, S.1    Seger, C.-J.2
  • 6
    • 0043198746 scopus 로고    scopus 로고
    • Proof engineering in the large: Formal verification of pentium®4 FP divider
    • R. Kaivola and K. Kohatsu, "Proof Engineering in the Large: Formal Verification of Pentium®4 FP Divider", CHARM 2001.
    • (2001) CHARM
    • Kaivola, R.1    Kohatsu, K.2
  • 7
    • 0043198744 scopus 로고    scopus 로고
    • Verification of pentium®4 multiplier with symbolic simulation & theorem proving
    • N. Narasimhan and R. Kaivola, "Verification of Pentium®4 Multiplier with Symbolic Simulation & Theorem Proving", DATE 2001.
    • (2001) DATE
    • Narasimhan, N.1    Kaivola, R.2
  • 11
    • 0035186885 scopus 로고    scopus 로고
    • Introduction to generalized symbolic trajectory evaluation
    • A revised version will appear in IEEE Transactions on VLSI
    • J. Yang and C.-J. H. Seger, "Introduction to Generalized Symbolic Trajectory Evaluation", International Conference on Computer Design (ICCD), 2001. A revised version will appear in IEEE Transactions on VLSI.
    • (2001) International Conference on Computer Design (ICCD)
    • Yang, J.1    Seger, C.-J.H.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.