Combining theorem proving and trajectory evaluation in an industrial environment

Proceedings - Design Automation Conference

Volumn , Issue , 1998, Pages 538-541

  Aagaard, Mark D ^a   Jones, Robert B ^a   Seger, Carl Johan H ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MODEL CHECKING; SPECIFICATIONS; COMPUTER SIMULATION; THEOREM PROVING;

GATE LEVELS; INDUSTRIAL ENVIRONMENTS;

THEOREM PROVING; REDUCED INSTRUCTION SET COMPUTING;

INSTRUCTION-LENGTH MARKERS (IM); SYMBOLIC TRAJECTORY EVALUATION (STE);

EID: 0031634235     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. M. D. Aagaard and C.-J. H. Seger. The formal verification of a pipelined double-precision IEEE floating-point multiplier. In ICCAD, pages 7-10. IEEE Comp. Soc. Press, Washington D.C. Nov. 1995.
2. A. Camelleri. A hybrid approach to verifying liveness in a symmetric multi-processor. In E. L. Gunter and A. Felty, editors, Theorem Proving in Higher Order Logics, pages 49-68. Springer Verlag; New York, Sept. 1997.
3. S. Hazelhurst and C.-J. H. Seger. A simple theorem prover based on symbolic trajectory evaluation and BDDs. IEEE Trans, on CAD, Apr. 1995.
4. Pentium Processor User's Manual, Volume 3: Architecture and Programming Manual. Intel Corporation, 1993.
5. J.-Y. Jang, S. Qadeer, M. Kaufmann, and C. Pixley. Formal verification of FIRE: A case study. In DAC, pages 173-177, June 1997.
6. J. Joyce and C.-J. Seger. Linking BDD based symbolic evaluation to interactive theorem proving. In DAC, pages 469-474, June 1993.
7. S. P. Miller and M. Srivas. Formal verification of the AAMP5 microprocessor: A case study in the industrial use of formal methods. In Workshop on Industrial-Strength Formal Specification Techniques, Apr. 1995.
8. C.-J. H. Seger and R. E. Bryant. Formal verification by symbolic evaluation of partially-ordered trajectories. Formal Methods in System Design, 6(2): 147, Mar. 1995.