Low clock-swing conditional-precharge flip-flop for more than 30% power reduction

Electronics Letters

Volumn 36, Issue 9, 2000, Pages 785-786

  Zhang, Yan ^a   Yang, Huazhong ^a   Wang, Hui ^a  

^a TSINGHUA UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC POWER SUPPLIES TO APPARATUS; LEAKAGE CURRENTS; MOSFET DEVICES; NAND CIRCUITS; THRESHOLD VOLTAGE; TIMING CIRCUITS;

LOW CLOCK SWING CONDITIONAL PRECHARGE FLIP FLOP; POWER REDUCTION;

FLIP FLOP CIRCUITS;

EID: 0033733412     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20000491     Document Type: Article

References (5)

1. CHANG, JUI-MING, and PEDRAM, M.: 'Energy minimization using multiple supply votages', IEEE Trans. VLSI Syst., 1997, 5, (4), pp. 436-443
2. KAWAGUCHI, H., and SAKURAI, T.: 'A reduced clock-swing flip-flop (RCSFF) for 63% power reduction', IEEE J. Solid-State Circuits, 1998, SC-33, (5), pp. 807-811
3. HOSSAIN, R., WRONSKI, L.D., and ALBICKI, A.: 'Low power design using double edge triggered flip-flop', IEEE Trans. VLSI Syst., 1994, 2, (2), pp. 261-265
4. KWON, YOUNG-SU, PARK, IN-CHEOL, and KYUNG, CHONG-MIN: 'A new single-clock flip-flop for half-swing clocking', IEICE Trans. Fundamentals, 1999, E82-A, (11), pp. 2521-2526
5. STOJANOVIC, V., and OKLOBZIJA, V.G.: 'Comparative analysis of master-slave latch and flip-flops for high-performance and low-power systems', IEEE J. Solid-State Circuits, 1999, 34, (4), pp. 536-548