A new reduced clock-swing flip-flop: NAND-type Keeper flip-flop (NDKFF)

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2002, Pages 129-132

  Tokumasu, Motoki ^a   Fujii, Hiroshige ^a   Ohta, Masako ^a   Fuse, Tsuneaki ^a   Kameyama, Atsushi ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CELLULAR TELEPHONE SYSTEMS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; NAND CIRCUITS; PERSONAL DIGITAL ASSISTANTS; POWER CONTROL; TIMING CIRCUITS; WAVEFORM ANALYSIS;

REDUCED CLOCK SWING FLIP FLOPS (RCSFF);

FLIP FLOP CIRCUITS;

EID: 0036053279     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Low-power circuit design for multimedia CMOS VLSI's
2. Half-swing clocking scheme for 75% power saving in clocking circuitry
3. A reduced clock-swing flip-flop (RCSFF) for 63% power reduction
4. A low-power half-swing clocking scheme for flip-flop with complementary gate and source drive
5. A new single-clock flip-flop for hall-swing clocking
6. Flow-through latch and edge-triggered flip-flop hybrid elements